Search

Ly D. Pham

Examiner (ID: 15722)

Most Active Art Unit
2827
Art Unit(s)
2827, 2818, 2713
Total Applications
2164
Issued Applications
2016
Pending Applications
83
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18174459 [patent_doc_number] => 11574173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Power efficient near memory analog multiply-and-accumulate (MAC) [patent_app_type] => utility [patent_app_number] => 16/721819 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4337 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721819 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/721819
Power efficient near memory analog multiply-and-accumulate (MAC) Dec 18, 2019 Issued
Array ( [id] => 16096431 [patent_doc_number] => 20200202202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => SYNAPSE CIRCUIT WITH MEMORY [patent_app_type] => utility [patent_app_number] => 16/719761 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6913 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719761 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/719761
Synapse circuit with memory Dec 17, 2019 Issued
Array ( [id] => 17150635 [patent_doc_number] => 11143706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Battery capacity estimation method and battery capacity estimation device [patent_app_type] => utility [patent_app_number] => 16/718829 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6762 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16718829 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/718829
Battery capacity estimation method and battery capacity estimation device Dec 17, 2019 Issued
Array ( [id] => 16904521 [patent_doc_number] => 20210183437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => PERPECTUAL DIGITAL PERCEPTRON [patent_app_type] => utility [patent_app_number] => 16/717444 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4041 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717444 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717444
Perpectual digital perceptron Dec 16, 2019 Issued
Array ( [id] => 16193897 [patent_doc_number] => 20200234746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => LOW STANDBY POWER WITH FAST TURN ON METHOD FOR NON-VOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/715412 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715412 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715412
Low standby power with fast turn on method for non-volatile memory devices Dec 15, 2019 Issued
Array ( [id] => 17606910 [patent_doc_number] => 11335402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Systems and techniques for accessing multiple memory cells concurrently [patent_app_type] => utility [patent_app_number] => 16/712682 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 21735 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16712682 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/712682
Systems and techniques for accessing multiple memory cells concurrently Dec 11, 2019 Issued
Array ( [id] => 15775207 [patent_doc_number] => 20200118621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => MULTI-LEVEL SELF-SELECTING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/711361 [patent_app_country] => US [patent_app_date] => 2019-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16711361 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/711361
Multi-level self-selecting memory device Dec 10, 2019 Issued
Array ( [id] => 17907790 [patent_doc_number] => 11461645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Initialization of memory networks [patent_app_type] => utility [patent_app_number] => 16/699814 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16699814 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/699814
Initialization of memory networks Dec 1, 2019 Issued
Array ( [id] => 15967773 [patent_doc_number] => 20200167638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => CIRCUIT NEURONAL APTE A METTRE EN OEUVRE UN APPRENTISSAGE SYNAPTIQUE [patent_app_type] => utility [patent_app_number] => 16/695588 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695588 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/695588
CIRCUIT NEURONAL APTE A METTRE EN OEUVRE UN APPRENTISSAGE SYNAPTIQUE Nov 25, 2019 Abandoned
Array ( [id] => 17237677 [patent_doc_number] => 11181552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Categorization of acquired data based on explicit and implicit means [patent_app_type] => utility [patent_app_number] => 16/695795 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3888 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695795 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/695795
Categorization of acquired data based on explicit and implicit means Nov 25, 2019 Issued
Array ( [id] => 15745253 [patent_doc_number] => 20200111516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => APPARATUS WITH A CALIBRATION MECHANISM [patent_app_type] => utility [patent_app_number] => 16/692306 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692306 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692306
Apparatus with a calibration mechanism Nov 21, 2019 Issued
Array ( [id] => 17106340 [patent_doc_number] => 11126557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Apparatuses and methods for cache operations [patent_app_type] => utility [patent_app_number] => 16/679553 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 25116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16679553 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/679553
Apparatuses and methods for cache operations Nov 10, 2019 Issued
Array ( [id] => 16879975 [patent_doc_number] => 11030124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Semiconductor device with secure access key and associated methods and systems [patent_app_type] => utility [patent_app_number] => 16/677376 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 17707 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16677376 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/677376
Semiconductor device with secure access key and associated methods and systems Nov 6, 2019 Issued
Array ( [id] => 17238428 [patent_doc_number] => 11182308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Semiconductor device with secure access key and associated methods and systems [patent_app_type] => utility [patent_app_number] => 16/677478 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 17710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16677478 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/677478
Semiconductor device with secure access key and associated methods and systems Nov 6, 2019 Issued
Array ( [id] => 16826539 [patent_doc_number] => 20210141832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => STORAGE OPTIMIZATION FOR PRODUCTS MANUFACTURING [patent_app_type] => utility [patent_app_number] => 16/676496 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16676496 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/676496
Storage optimization for products manufacturing Nov 6, 2019 Issued
Array ( [id] => 17351583 [patent_doc_number] => 11226213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Capacitive proximity sensor [patent_app_type] => utility [patent_app_number] => 16/665131 [patent_app_country] => US [patent_app_date] => 2019-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5823 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16665131 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/665131
Capacitive proximity sensor Oct 27, 2019 Issued
Array ( [id] => 15503975 [patent_doc_number] => 20200052176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => INTERCONNECTION BY LATERAL TRANSFER PRINTING [patent_app_type] => utility [patent_app_number] => 16/660776 [patent_app_country] => US [patent_app_date] => 2019-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16660776 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/660776
Interconnection by lateral transfer printing Oct 21, 2019 Issued
Array ( [id] => 16193920 [patent_doc_number] => 20200234769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => MEMORY AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/657104 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657104 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/657104
Memory and operation method thereof Oct 17, 2019 Issued
Array ( [id] => 16659119 [patent_doc_number] => 20210055756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => CONNECTION INTERFACE CIRCUIT, MEMORY STORAGE DEVICE AND SIGNAL GENERATION METHOD [patent_app_type] => utility [patent_app_number] => 16/656524 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16656524 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/656524
Connection interface circuit, memory storage device and signal generation method Oct 16, 2019 Issued
Array ( [id] => 15837679 [patent_doc_number] => 20200134122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => INTEGRATED CIRCUIT FIN LAYOUT METHOD, SYSTEM, AND STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/599552 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599552 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599552
Integrated circuit fin layout method, system, and structure Oct 10, 2019 Issued
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