Search

Ly D. Pham

Examiner (ID: 15722)

Most Active Art Unit
2827
Art Unit(s)
2827, 2818, 2713
Total Applications
2164
Issued Applications
2016
Pending Applications
83
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13334447 [patent_doc_number] => 20180218761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => SYSTEMS AND METHODS OF PIPELINED OUTPUT LATCHING INVOLVING SYNCHRONOUS MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 15/933291 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933291 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/933291
Systems and methods of pipelined output latching involving synchronous memory arrays Mar 21, 2018 Issued
Array ( [id] => 14841935 [patent_doc_number] => 20190279368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => Method and Apparatus for Multi-Model Primitive Fitting based on Deep Geometric Boundary and Instance Aware Segmentation [patent_app_type] => utility [patent_app_number] => 15/912738 [patent_app_country] => US [patent_app_date] => 2018-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15912738 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/912738
Method and apparatus for multi-model primitive fitting based on deep geometric boundary and instance aware segmentation Mar 5, 2018 Issued
Array ( [id] => 16434741 [patent_doc_number] => 10834853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Electronic device with a card-level thermal regulator mechanism and associated systems, devices, and methods [patent_app_type] => utility [patent_app_number] => 15/910612 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6308 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910612 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910612
Electronic device with a card-level thermal regulator mechanism and associated systems, devices, and methods Mar 1, 2018 Issued
Array ( [id] => 15375387 [patent_doc_number] => 10529420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Memory write driver, method and system [patent_app_type] => utility [patent_app_number] => 15/904848 [patent_app_country] => US [patent_app_date] => 2018-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 36 [patent_no_of_words] => 12330 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904848 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/904848
Memory write driver, method and system Feb 25, 2018 Issued
Array ( [id] => 13740771 [patent_doc_number] => 20180374855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => Apparatuses Having Body Connection Lines Coupled with Access Devices [patent_app_type] => utility [patent_app_number] => 15/895928 [patent_app_country] => US [patent_app_date] => 2018-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4986 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15895928 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/895928
Apparatuses having body connection lines coupled with access devices Feb 12, 2018 Issued
Array ( [id] => 16308462 [patent_doc_number] => 10777267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => High speed thin film two terminal resistive memory [patent_app_type] => utility [patent_app_number] => 15/864148 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5653 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15864148 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/864148
High speed thin film two terminal resistive memory Jan 7, 2018 Issued
Array ( [id] => 12691858 [patent_doc_number] => 20180122452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => HALF DENSITY FERROELECTRIC MEMORY AND OPERATION [patent_app_type] => utility [patent_app_number] => 15/854529 [patent_app_country] => US [patent_app_date] => 2017-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854529 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/854529
Half density ferroelectric memory and operation Dec 25, 2017 Issued
Array ( [id] => 17136935 [patent_doc_number] => 11138493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => Approaching homeostasis in a binary neural network [patent_app_type] => utility [patent_app_number] => 15/853280 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7826 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15853280 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/853280
Approaching homeostasis in a binary neural network Dec 21, 2017 Issued
Array ( [id] => 14472255 [patent_doc_number] => 20190187771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => REDUCING POWER CONSUMPTION IN A NEURAL NETWORK ENVIRONMENT USING DATA MANAGEMENT [patent_app_type] => utility [patent_app_number] => 15/847785 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15847785 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/847785
Reducing power consumption in a neural network environment using data management Dec 18, 2017 Issued
Array ( [id] => 13485469 [patent_doc_number] => 20180294277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 15/844188 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844188 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/844188
Three dimensional semiconductor memory devices Dec 14, 2017 Issued
Array ( [id] => 15077187 [patent_doc_number] => 10468088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Redundant voltage regulator for memory devices [patent_app_type] => utility [patent_app_number] => 15/843480 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9455 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15843480 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/843480
Redundant voltage regulator for memory devices Dec 14, 2017 Issued
Array ( [id] => 14475115 [patent_doc_number] => 20190189203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => MULTI-LEVEL SELF-SELECTING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/842496 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15842496 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/842496
Multi-level self-selecting memory device Dec 13, 2017 Issued
Array ( [id] => 14475121 [patent_doc_number] => 20190189206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/842504 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15842504 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/842504
Techniques to access a self-selecting memory device Dec 13, 2017 Issued
Array ( [id] => 14444599 [patent_doc_number] => 20190180173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => METHOD AND APPARATUS FOR USING REFERENCE RESISTOR IN ONE-TIME PROGRAMMABLE MEMORY OF AN ARTIFICIAL INTELLIGENCE INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/838131 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15838131 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/838131
METHOD AND APPARATUS FOR USING REFERENCE RESISTOR IN ONE-TIME PROGRAMMABLE MEMORY OF AN ARTIFICIAL INTELLIGENCE INTEGRATED CIRCUIT Dec 10, 2017 Abandoned
Array ( [id] => 16802543 [patent_doc_number] => 10997492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Automated methods for conversions to a lower precision data format [patent_app_type] => utility [patent_app_number] => 15/838273 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5000 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15838273 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/838273
Automated methods for conversions to a lower precision data format Dec 10, 2017 Issued
Array ( [id] => 13498141 [patent_doc_number] => 20180300613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => PROCESSING DISCONTIGUOUS MEMORY AS CONTIGUOUS MEMORY TO IMPROVE PERFORMANCE OF A NEURAL NETWORK ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 15/829832 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15829832 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/829832
Processing discontiguous memory as contiguous memory to improve performance of a neural network environment Nov 30, 2017 Issued
Array ( [id] => 12776776 [patent_doc_number] => 20180150760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => EMULATION OF QUANTUM AND QUANTUM-INSPIRED DISCRETE-STATE SYSTEMS WITH CLASSICAL TRANSCONDUCTOR-CAPACITOR CIRCUITS [patent_app_type] => utility [patent_app_number] => 15/826100 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826100 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826100
Emulation of quantum and quantum-inspired discrete-state systems with classical transconductor-capacitor circuits Nov 28, 2017 Issued
Array ( [id] => 14380243 [patent_doc_number] => 20190164034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => SHORT DEPTH CIRCUITS AS QUANTUM CLASSIFIERS [patent_app_type] => utility [patent_app_number] => 15/826327 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826327 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826327
Short depth circuits as quantum classifiers Nov 28, 2017 Issued
Array ( [id] => 13907409 [patent_doc_number] => 20190042909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => RECONFIGURABLE NEURO-SYNAPTIC CORES FOR SPIKING NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 15/821123 [patent_app_country] => US [patent_app_date] => 2017-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15821123 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/821123
Reconfigurable neuro-synaptic cores for spiking neural network Nov 21, 2017 Issued
Array ( [id] => 14737927 [patent_doc_number] => 10388372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => 1T-1R architecture for resistive random access memory [patent_app_type] => utility [patent_app_number] => 15/817887 [patent_app_country] => US [patent_app_date] => 2017-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 5332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817887 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/817887
1T-1R architecture for resistive random access memory Nov 19, 2017 Issued
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