
Ly D. Pham
Examiner (ID: 15722)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827, 2818, 2713 |
| Total Applications | 2164 |
| Issued Applications | 2016 |
| Pending Applications | 83 |
| Abandoned Applications | 106 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13723657
[patent_doc_number] => 20170372784
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-28
[patent_title] => CONNECTING MEMORY CELLS TO A DATA LINE SEQUENTIALLY WHILE APPLYING A PROGRAM VOLTAGE TO THE MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 15/692565
[patent_app_country] => US
[patent_app_date] => 2017-08-31
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/692565 | Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells | Aug 30, 2017 | Issued |
Array
(
[id] => 12235842
[patent_doc_number] => 20180068705
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[patent_kind] => A1
[patent_issue_date] => 2018-03-08
[patent_title] => 'REDUNDANCY ARRAY COLUMN DECODER FOR MEMORY'
[patent_app_type] => utility
[patent_app_number] => 15/689940
[patent_app_country] => US
[patent_app_date] => 2017-08-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/689940 | Redundancy array column decoder for memory | Aug 28, 2017 | Issued |
Array
(
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[patent_doc_number] => 10497692
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[patent_kind] => B2
[patent_issue_date] => 2019-12-03
[patent_title] => SRAM structure with alternate gate pitches
[patent_app_type] => utility
[patent_app_number] => 15/689934
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Array
(
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[patent_issue_date] => 2017-12-07
[patent_title] => 'MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE'
[patent_app_type] => utility
[patent_app_number] => 15/686416
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[patent_app_date] => 2017-08-25
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/686416 | Memory array with power-efficient read architecture | Aug 24, 2017 | Issued |
Array
(
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[patent_doc_number] => 20170345484
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[patent_kind] => A1
[patent_issue_date] => 2017-11-30
[patent_title] => SEMICONDUCTOR MEMORY DEVICE THAT PERFORMS A REFRESH OPERATION
[patent_app_type] => utility
[patent_app_number] => 15/678436
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/678436 | Semiconductor memory device that includes a refresh control circuit that maintains a refresh cycle when an MRS code signal is changed due to temperature | Aug 15, 2017 | Issued |
Array
(
[id] => 13187615
[patent_doc_number] => 10109333
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[patent_issue_date] => 2018-10-23
[patent_title] => Nonvolatile logic and security circuits
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Array
(
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[patent_doc_number] => 10459831
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[patent_issue_date] => 2019-10-29
[patent_title] => Non-transitory computer-readable storage medium, data specification method, and data specification device
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/653682 | Non-transitory computer-readable storage medium, data specification method, and data specification device | Jul 18, 2017 | Issued |
Array
(
[id] => 11997226
[patent_doc_number] => 20170301380
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[patent_issue_date] => 2017-10-19
[patent_title] => 'SEMICONDUCTOR DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/635550 | SEMICONDUCTOR DEVICE | Jun 27, 2017 | Abandoned |
Array
(
[id] => 11996391
[patent_doc_number] => 20170300546
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[patent_kind] => A1
[patent_issue_date] => 2017-10-19
[patent_title] => 'Method and Apparatus for Data Processing in Data Modeling'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/631864 | Method and apparatus for data processing in data modeling | Jun 22, 2017 | Issued |
Array
(
[id] => 13716155
[patent_doc_number] => 20170369032
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-28
[patent_title] => SYSTEMS AND METHODS FOR MACHINE SENSING AND COMMUNICATION
[patent_app_type] => utility
[patent_app_number] => 15/630743
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[patent_app_date] => 2017-06-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/630743 | Systems and methods for machine sensing and communication | Jun 21, 2017 | Issued |
Array
(
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[patent_doc_number] => 20170287529
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[patent_issue_date] => 2017-10-05
[patent_title] => 'APPARATUSES AND METHODS FOR COMPENSATING FOR PROCESS, VOLTAGE, AND TEMPERATURE VARIATION IN A MEMORY'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/627242 | Apparatuses and methods for compensating for process, voltage, and temperature variation in a memory | Jun 18, 2017 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/599041 | Semiconductor device | May 17, 2017 | Issued |
Array
(
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[patent_issue_date] => 2020-06-09
[patent_title] => Manufacturing method for forming a thin film between two terminals
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Array
(
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[patent_title] => 'TFD I/O Partition for High-Speed, High-Density Applications'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/595163 | TFD I/O partition for high-speed, high-density applications | May 14, 2017 | Issued |
Array
(
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[patent_title] => 'METHODS AND APPARATUSES INCLUDING COMMAND DELAY ADJUSTMENT CIRCUIT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/595056 | Methods and apparatuses including command delay adjustment circuit | May 14, 2017 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/588848 | Semiconductor memory device and memory system | May 7, 2017 | Issued |
Array
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[patent_title] => MONITORING OF HEATED TUBES
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[rel_patent_id] =>[rel_patent_doc_number] =>) 16/095736 | Monitoring of heated tubes | May 2, 2017 | Issued |
Array
(
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[patent_title] => 'METHODS AND SYSTEMS TO SELECTIVELY BOOST AN OPERATING VOLTAGE OF, AND CONTROLS TO AN 8T BIT-CELL ARRAY AND/OR OTHER LOGIC BLOCKS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/495954 | Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks | Apr 23, 2017 | Issued |
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/479119 | COMPUTER-IMPLEMENTED METHOD OF DESIGNING AN INTEGRATED CIRCUIT | Apr 3, 2017 | Abandoned |