Search

Ly D. Pham

Examiner (ID: 15722)

Most Active Art Unit
2827
Art Unit(s)
2827, 2818, 2713
Total Applications
2164
Issued Applications
2016
Pending Applications
83
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13723657 [patent_doc_number] => 20170372784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => CONNECTING MEMORY CELLS TO A DATA LINE SEQUENTIALLY WHILE APPLYING A PROGRAM VOLTAGE TO THE MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 15/692565 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15692565 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/692565
Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells Aug 30, 2017 Issued
Array ( [id] => 12235842 [patent_doc_number] => 20180068705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'REDUNDANCY ARRAY COLUMN DECODER FOR MEMORY' [patent_app_type] => utility [patent_app_number] => 15/689940 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15689940 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/689940
Redundancy array column decoder for memory Aug 28, 2017 Issued
Array ( [id] => 15200379 [patent_doc_number] => 10497692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => SRAM structure with alternate gate pitches [patent_app_type] => utility [patent_app_number] => 15/689934 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3250 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15689934 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/689934
SRAM structure with alternate gate pitches Aug 28, 2017 Issued
Array ( [id] => 12095328 [patent_doc_number] => 20170352421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 15/686416 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6390 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686416 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686416
Memory array with power-efficient read architecture Aug 24, 2017 Issued
Array ( [id] => 12989275 [patent_doc_number] => 20170345484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => SEMICONDUCTOR MEMORY DEVICE THAT PERFORMS A REFRESH OPERATION [patent_app_type] => utility [patent_app_number] => 15/678436 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678436 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678436
Semiconductor memory device that includes a refresh control circuit that maintains a refresh cycle when an MRS code signal is changed due to temperature Aug 15, 2017 Issued
Array ( [id] => 13187615 [patent_doc_number] => 10109333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => Nonvolatile logic and security circuits [patent_app_type] => utility [patent_app_number] => 15/672469 [patent_app_country] => US [patent_app_date] => 2017-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10575 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15672469 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/672469
Nonvolatile logic and security circuits Aug 8, 2017 Issued
Array ( [id] => 15059051 [patent_doc_number] => 10459831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Non-transitory computer-readable storage medium, data specification method, and data specification device [patent_app_type] => utility [patent_app_number] => 15/653682 [patent_app_country] => US [patent_app_date] => 2017-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12178 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15653682 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/653682
Non-transitory computer-readable storage medium, data specification method, and data specification device Jul 18, 2017 Issued
Array ( [id] => 11997226 [patent_doc_number] => 20170301380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/635550 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 33528 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15635550 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/635550
SEMICONDUCTOR DEVICE Jun 27, 2017 Abandoned
Array ( [id] => 11996391 [patent_doc_number] => 20170300546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'Method and Apparatus for Data Processing in Data Modeling' [patent_app_type] => utility [patent_app_number] => 15/631864 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 11603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15631864 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/631864
Method and apparatus for data processing in data modeling Jun 22, 2017 Issued
Array ( [id] => 13716155 [patent_doc_number] => 20170369032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => SYSTEMS AND METHODS FOR MACHINE SENSING AND COMMUNICATION [patent_app_type] => utility [patent_app_number] => 15/630743 [patent_app_country] => US [patent_app_date] => 2017-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15630743 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/630743
Systems and methods for machine sensing and communication Jun 21, 2017 Issued
Array ( [id] => 11983374 [patent_doc_number] => 20170287529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'APPARATUSES AND METHODS FOR COMPENSATING FOR PROCESS, VOLTAGE, AND TEMPERATURE VARIATION IN A MEMORY' [patent_app_type] => utility [patent_app_number] => 15/627242 [patent_app_country] => US [patent_app_date] => 2017-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627242 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627242
Apparatuses and methods for compensating for process, voltage, and temperature variation in a memory Jun 18, 2017 Issued
Array ( [id] => 12477153 [patent_doc_number] => 09990970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/599041 [patent_app_country] => US [patent_app_date] => 2017-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5636 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599041 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/599041
Semiconductor device May 17, 2017 Issued
Array ( [id] => 16034837 [patent_doc_number] => 10679850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Manufacturing method for forming a thin film between two terminals [patent_app_type] => utility [patent_app_number] => 16/303689 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 18192 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16303689 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/303689
Manufacturing method for forming a thin film between two terminals May 16, 2017 Issued
Array ( [id] => 12033568 [patent_doc_number] => 20170323667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'TFD I/O Partition for High-Speed, High-Density Applications' [patent_app_type] => utility [patent_app_number] => 15/595163 [patent_app_country] => US [patent_app_date] => 2017-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 15222 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15595163 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/595163
TFD I/O partition for high-speed, high-density applications May 14, 2017 Issued
Array ( [id] => 12005168 [patent_doc_number] => 20170309323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'METHODS AND APPARATUSES INCLUDING COMMAND DELAY ADJUSTMENT CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/595056 [patent_app_country] => US [patent_app_date] => 2017-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5264 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15595056 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/595056
Methods and apparatuses including command delay adjustment circuit May 14, 2017 Issued
Array ( [id] => 11939504 [patent_doc_number] => 20170243654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/588848 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 15709 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15588848 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/588848
Semiconductor memory device and memory system May 7, 2017 Issued
Array ( [id] => 16392333 [patent_doc_number] => 20200333274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => MONITORING OF HEATED TUBES [patent_app_type] => utility [patent_app_number] => 16/095736 [patent_app_country] => US [patent_app_date] => 2017-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16095736 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/095736
Monitoring of heated tubes May 2, 2017 Issued
Array ( [id] => 11939487 [patent_doc_number] => 20170243637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'METHODS AND SYSTEMS TO SELECTIVELY BOOST AN OPERATING VOLTAGE OF, AND CONTROLS TO AN 8T BIT-CELL ARRAY AND/OR OTHER LOGIC BLOCKS' [patent_app_type] => utility [patent_app_number] => 15/495954 [patent_app_country] => US [patent_app_date] => 2017-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6056 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15495954 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/495954
Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks Apr 23, 2017 Issued
Array ( [id] => 13016867 [patent_doc_number] => 10031548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Latency control device and semiconductor device including the same [patent_app_type] => utility [patent_app_number] => 15/482206 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4845 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15482206 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/482206
Latency control device and semiconductor device including the same Apr 6, 2017 Issued
Array ( [id] => 12986980 [patent_doc_number] => 20170344692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => COMPUTER-IMPLEMENTED METHOD OF DESIGNING AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/479119 [patent_app_country] => US [patent_app_date] => 2017-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15479119 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/479119
COMPUTER-IMPLEMENTED METHOD OF DESIGNING AN INTEGRATED CIRCUIT Apr 3, 2017 Abandoned
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