Search

Ly D. Pham

Examiner (ID: 15722)

Most Active Art Unit
2827
Art Unit(s)
2827, 2818, 2713
Total Applications
2164
Issued Applications
2016
Pending Applications
83
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11760071 [patent_doc_number] => 20170206940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/184064 [patent_app_country] => US [patent_app_date] => 2016-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6009 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15184064 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/184064
Semiconductor device Jun 15, 2016 Issued
Array ( [id] => 11615314 [patent_doc_number] => 09653176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Read disturb reclaim policy' [patent_app_type] => utility [patent_app_number] => 15/184878 [patent_app_country] => US [patent_app_date] => 2016-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15184878 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/184878
Read disturb reclaim policy Jun 15, 2016 Issued
Array ( [id] => 11753226 [patent_doc_number] => 09711244 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-18 [patent_title] => 'Memory circuit' [patent_app_type] => utility [patent_app_number] => 15/182178 [patent_app_country] => US [patent_app_date] => 2016-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1876 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15182178 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/182178
Memory circuit Jun 13, 2016 Issued
Array ( [id] => 12174631 [patent_doc_number] => 09892776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Half density ferroelectric memory and operation' [patent_app_type] => utility [patent_app_number] => 15/181188 [patent_app_country] => US [patent_app_date] => 2016-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13236 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15181188 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/181188
Half density ferroelectric memory and operation Jun 12, 2016 Issued
Array ( [id] => 11339384 [patent_doc_number] => 20160365140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL AND SENSE AMPLIFER, AND IC CARD INCLUDING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/166152 [patent_app_country] => US [patent_app_date] => 2016-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13179 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15166152 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/166152
Semiconductor device including memory cell and sense amplifer, and IC card including semiconductor device May 25, 2016 Issued
Array ( [id] => 11564429 [patent_doc_number] => 09627020 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-18 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 15/165238 [patent_app_country] => US [patent_app_date] => 2016-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4094 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15165238 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/165238
Semiconductor device May 25, 2016 Issued
Array ( [id] => 13640301 [patent_doc_number] => 09847111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-19 [patent_title] => Systems and methods of pipelined output latching involving synchronous memory arrays [patent_app_type] => utility [patent_app_number] => 15/159452 [patent_app_country] => US [patent_app_date] => 2016-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 9296 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15159452 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/159452
Systems and methods of pipelined output latching involving synchronous memory arrays May 18, 2016 Issued
Array ( [id] => 11063513 [patent_doc_number] => 20160260475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'MULTIPORT MEMORY CELL HAVING IMPROVED DENSITY AREA' [patent_app_type] => utility [patent_app_number] => 15/157158 [patent_app_country] => US [patent_app_date] => 2016-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15157158 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/157158
MULTIPORT MEMORY CELL HAVING IMPROVED DENSITY AREA May 16, 2016 Abandoned
Array ( [id] => 12040517 [patent_doc_number] => 09818752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Memory metal scheme' [patent_app_type] => utility [patent_app_number] => 15/153872 [patent_app_country] => US [patent_app_date] => 2016-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 6067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15153872 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/153872
Memory metal scheme May 12, 2016 Issued
Array ( [id] => 11652627 [patent_doc_number] => 20170148528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/150284 [patent_app_country] => US [patent_app_date] => 2016-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15150284 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/150284
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME May 8, 2016 Abandoned
Array ( [id] => 11811333 [patent_doc_number] => 09715907 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-25 [patent_title] => 'Optimal data eye for improved Vref margin' [patent_app_type] => utility [patent_app_number] => 15/150334 [patent_app_country] => US [patent_app_date] => 2016-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6015 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15150334 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/150334
Optimal data eye for improved Vref margin May 8, 2016 Issued
Array ( [id] => 11057079 [patent_doc_number] => 20160254041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'NONVOLATILE LOGIC AND SECURITY CIRCUITS' [patent_app_type] => utility [patent_app_number] => 15/149826 [patent_app_country] => US [patent_app_date] => 2016-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10738 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15149826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/149826
Nonvolatile logic and security circuits May 8, 2016 Issued
Array ( [id] => 11681079 [patent_doc_number] => 09679613 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-13 [patent_title] => 'TFD I/O partition for high-speed, high-density applications' [patent_app_type] => utility [patent_app_number] => 15/148726 [patent_app_country] => US [patent_app_date] => 2016-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 15180 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15148726 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/148726
TFD I/O partition for high-speed, high-density applications May 5, 2016 Issued
Array ( [id] => 11551346 [patent_doc_number] => 09620201 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-11 [patent_title] => 'Storage system and method for using hybrid blocks with sub-block erase operations' [patent_app_type] => utility [patent_app_number] => 15/138984 [patent_app_country] => US [patent_app_date] => 2016-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5277 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15138984 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/138984
Storage system and method for using hybrid blocks with sub-block erase operations Apr 25, 2016 Issued
Array ( [id] => 11510007 [patent_doc_number] => 09601170 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-21 [patent_title] => 'Apparatuses and methods for adjusting a delay of a command signal path' [patent_app_type] => utility [patent_app_number] => 15/139120 [patent_app_country] => US [patent_app_date] => 2016-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15139120 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/139120
Apparatuses and methods for adjusting a delay of a command signal path Apr 25, 2016 Issued
Array ( [id] => 12108830 [patent_doc_number] => 09865317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-09 [patent_title] => 'Methods and apparatuses including command delay adjustment circuit' [patent_app_type] => utility [patent_app_number] => 15/139102 [patent_app_country] => US [patent_app_date] => 2016-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5234 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15139102 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/139102
Methods and apparatuses including command delay adjustment circuit Apr 25, 2016 Issued
Array ( [id] => 11430795 [patent_doc_number] => 09569111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Memory system' [patent_app_type] => utility [patent_app_number] => 15/135953 [patent_app_country] => US [patent_app_date] => 2016-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 11579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15135953 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/135953
Memory system Apr 21, 2016 Issued
Array ( [id] => 11564433 [patent_doc_number] => 09627025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Memory device and memory system including the same' [patent_app_type] => utility [patent_app_number] => 15/134170 [patent_app_country] => US [patent_app_date] => 2016-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 12808 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15134170 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/134170
Memory device and memory system including the same Apr 19, 2016 Issued
Array ( [id] => 11391607 [patent_doc_number] => 09552856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-24 [patent_title] => 'Memory timing self-calibration' [patent_app_type] => utility [patent_app_number] => 15/095347 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15095347 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/095347
Memory timing self-calibration Apr 10, 2016 Issued
Array ( [id] => 11020896 [patent_doc_number] => 20160217850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'METAL-INSULATOR PHASE TRANSITION FLIP-FLOP' [patent_app_type] => utility [patent_app_number] => 15/085543 [patent_app_country] => US [patent_app_date] => 2016-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8831 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15085543 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/085543
METAL-INSULATOR PHASE TRANSITION FLIP-FLOP Mar 29, 2016 Abandoned
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