Search

Ly D. Pham

Examiner (ID: 490, Phone: (571)272-1793 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2713, 2818, 2827
Total Applications
2205
Issued Applications
2049
Pending Applications
85
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19452417 [patent_doc_number] => 20240312547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR STORING ERROR INFORMATION AND PROVIDING RECOMMENDATIONS BASED ON SAME [patent_app_type] => utility [patent_app_number] => 18/598937 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18598937 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/598937
Apparatuses, systems, and methods for storing error information and providing recommendations based on same Mar 6, 2024 Issued
Array ( [id] => 19269055 [patent_doc_number] => 20240212759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY DEVICE AND OPERATION THEREOF [patent_app_type] => utility [patent_app_number] => 18/595909 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595909 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/595909
Memory device and operation thereof Mar 4, 2024 Issued
Array ( [id] => 19834072 [patent_doc_number] => 20250085858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => BIT-LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/591238 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591238
BIT-LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME Feb 28, 2024 Pending
Array ( [id] => 19531478 [patent_doc_number] => 20240355380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => RAPID TAG INVALIDATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/582782 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582782 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/582782
RAPID TAG INVALIDATION CIRCUIT Feb 20, 2024 Pending
Array ( [id] => 19392530 [patent_doc_number] => 20240282400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => DIFFERENTIAL STROBE FAULT IDENTIFICATION [patent_app_type] => utility [patent_app_number] => 18/443948 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443948 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443948
DIFFERENTIAL STROBE FAULT IDENTIFICATION Feb 15, 2024 Issued
Array ( [id] => 20441298 [patent_doc_number] => 12512138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Magnetic memory [patent_app_type] => utility [patent_app_number] => 18/439612 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 4713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439612 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439612
Magnetic memory Feb 11, 2024 Issued
Array ( [id] => 19811362 [patent_doc_number] => 12242756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Tri-state electrical information storage [patent_app_type] => utility [patent_app_number] => 18/438807 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 36059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438807 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438807
Tri-state electrical information storage Feb 11, 2024 Issued
Array ( [id] => 20454605 [patent_doc_number] => 12517658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Rising edge detection of a closing cycle for a multi-cycle operation [patent_app_type] => utility [patent_app_number] => 18/436379 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436379 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436379
Rising edge detection of a closing cycle for a multi-cycle operation Feb 7, 2024 Issued
Array ( [id] => 19434688 [patent_doc_number] => 20240303186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/437038 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437038 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437038
Semiconductor storage device Feb 7, 2024 Issued
Array ( [id] => 19366084 [patent_doc_number] => 20240268118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => Memory Circuitry And Methods Used In Forming Memory Circuitry [patent_app_type] => utility [patent_app_number] => 18/435116 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435116 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435116
Memory circuitry and methods used in forming memory circuitry Feb 6, 2024 Issued
Array ( [id] => 19205858 [patent_doc_number] => 20240177757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => MEMORY DEVICES, CIRCUITS AND METHODS OF ADJUSTING A SENSING CURRENT FOR THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/434752 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434752 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/434752
Memory devices, circuits and methods of adjusting a sensing current for the memory device Feb 5, 2024 Issued
Array ( [id] => 19175852 [patent_doc_number] => 20240161826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => TERNARY CONTENT ADDRESSABLE MEMORY AND DECISION GENERATION METHOD FOR THE SAME [patent_app_type] => utility [patent_app_number] => 18/420874 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420874 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420874
Ternary content addressable memory and decision generation method for the same Jan 23, 2024 Issued
Array ( [id] => 20359930 [patent_doc_number] => 12475934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Memory device and method for operating memory device [patent_app_type] => utility [patent_app_number] => 18/415960 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5835 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415960 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415960
Memory device and method for operating memory device Jan 17, 2024 Issued
Array ( [id] => 20667363 [patent_doc_number] => 12609143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Read operations for a memory array and register [patent_app_type] => utility [patent_app_number] => 18/416770 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8728 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416770 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416770
Read operations for a memory array and register Jan 17, 2024 Issued
Array ( [id] => 20666541 [patent_doc_number] => 12608316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Sense amplifiers as static random access memory cache [patent_app_type] => utility [patent_app_number] => 18/414640 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18414640 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/414640
Sense amplifiers as static random access memory cache Jan 16, 2024 Issued
Array ( [id] => 19160842 [patent_doc_number] => 20240153549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => 2-PORT SRAM COMPRISING A CFET [patent_app_type] => utility [patent_app_number] => 18/413959 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413959 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/413959
2-port SRAM comprising a CFET Jan 15, 2024 Issued
Array ( [id] => 20673142 [patent_doc_number] => 12613653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-28 [patent_title] => Low pass through voltage on lower tier wordlines for read disturb improvement [patent_app_type] => utility [patent_app_number] => 18/412010 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9979 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412010 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/412010
Low pass through voltage on lower tier wordlines for read disturb improvement Jan 11, 2024 Issued
Array ( [id] => 20611018 [patent_doc_number] => 12586622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Digital device having a reset pad circuit that may be subject to hacker attack [patent_app_type] => utility [patent_app_number] => 18/410049 [patent_app_country] => US [patent_app_date] => 2024-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 2047 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18410049 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/410049
Digital device having a reset pad circuit that may be subject to hacker attack Jan 10, 2024 Issued
Array ( [id] => 19466247 [patent_doc_number] => 20240319917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/409481 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409481 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409481
Memory system Jan 9, 2024 Issued
Array ( [id] => 19993728 [patent_doc_number] => 20250131950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => MEMORY DEVICES, OPERATION METHODS THEREOF, AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/409430 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409430 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409430
Memory devices, operation methods thereof, and memory systems Jan 9, 2024 Issued
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