Search

Ly D. Pham

Examiner (ID: 15722)

Most Active Art Unit
2827
Art Unit(s)
2827, 2818, 2713
Total Applications
2164
Issued Applications
2016
Pending Applications
83
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9718592 [patent_doc_number] => 20140254290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'Local Evaluation Circuit for Static Random-Access Memory' [patent_app_type] => utility [patent_app_number] => 13/786860 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13786860 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/786860
Local evaluation circuit for static random-access memory Mar 5, 2013 Issued
Array ( [id] => 9210839 [patent_doc_number] => 20140010016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 13/787294 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4524 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13787294 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/787294
Nonvolatile semiconductor memory device and operation method of the same Mar 5, 2013 Issued
Array ( [id] => 9583900 [patent_doc_number] => 08773905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-08 [patent_title] => 'Identifying and mitigating restricted sampling voltage ranges in analog memory cells' [patent_app_type] => utility [patent_app_number] => 13/786792 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 8768 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13786792 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/786792
Identifying and mitigating restricted sampling voltage ranges in analog memory cells Mar 5, 2013 Issued
Array ( [id] => 9718538 [patent_doc_number] => 20140254236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'MEMORY STATE SENSING BASED ON CELL CAPACITANCE' [patent_app_type] => utility [patent_app_number] => 13/785602 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2704 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13785602 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/785602
Memory state sensing based on cell capacitance Mar 4, 2013 Issued
Array ( [id] => 10833090 [patent_doc_number] => 08861269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Internal data load for non-volatile storage' [patent_app_type] => utility [patent_app_number] => 13/786190 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 15420 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13786190 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/786190
Internal data load for non-volatile storage Mar 4, 2013 Issued
Array ( [id] => 9779682 [patent_doc_number] => 08854896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/785666 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 59 [patent_no_of_words] => 20116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13785666 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/785666
Nonvolatile semiconductor memory device Mar 4, 2013 Issued
Array ( [id] => 9361892 [patent_doc_number] => 20140071765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 13/786003 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13786003 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/786003
Semiconductor memory device and control method of the same Mar 4, 2013 Issued
Array ( [id] => 9014911 [patent_doc_number] => 20130229875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'METHOD OF READING AND WRITING NONVOLATILE MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 13/786202 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12005 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13786202 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/786202
Method of reading and writing nonvolatile memory cells Mar 4, 2013 Issued
Array ( [id] => 9047958 [patent_doc_number] => 08542513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-24 [patent_title] => 'Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells' [patent_app_type] => utility [patent_app_number] => 13/777083 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 49 [patent_no_of_words] => 10855 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13777083 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/777083
Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells Feb 25, 2013 Issued
Array ( [id] => 10833070 [patent_doc_number] => 08861249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Circuit and system of a low density one-time programmable memory' [patent_app_type] => utility [patent_app_number] => 13/761048 [patent_app_country] => US [patent_app_date] => 2013-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 6425 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761048 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761048
Circuit and system of a low density one-time programmable memory Feb 5, 2013 Issued
Array ( [id] => 9985165 [patent_doc_number] => 09030893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-12 [patent_title] => 'Write driver for write assistance in memory device' [patent_app_type] => utility [patent_app_number] => 13/760988 [patent_app_country] => US [patent_app_date] => 2013-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7171 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13760988 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/760988
Write driver for write assistance in memory device Feb 5, 2013 Issued
Array ( [id] => 9824788 [patent_doc_number] => 08934280 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-13 [patent_title] => 'Capacitive discharge programming for two-terminal memory cells' [patent_app_type] => utility [patent_app_number] => 13/761132 [patent_app_country] => US [patent_app_date] => 2013-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761132 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761132
Capacitive discharge programming for two-terminal memory cells Feb 5, 2013 Issued
Array ( [id] => 9002017 [patent_doc_number] => 20130223142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => '3D STACKED NAND FLASH MEMORY ARRAY ENABLING TO OPERATE BY LSM AND OPERATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/760320 [patent_app_country] => US [patent_app_date] => 2013-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4608 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13760320 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/760320
3D stacked NAND flash memory array enabling to operate by LSM and operation method thereof Feb 5, 2013 Issued
Array ( [id] => 9640906 [patent_doc_number] => 20140219016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'SYSTEM AND METHOD OF PROGRAMMING A MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 13/759344 [patent_app_country] => US [patent_app_date] => 2013-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14471 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13759344 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/759344
System and method of programming a memory cell Feb 4, 2013 Issued
Array ( [id] => 9640904 [patent_doc_number] => 20140219015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'SYSTEM AND METHOD OF PROGRAMMING A MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 13/759310 [patent_app_country] => US [patent_app_date] => 2013-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12646 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13759310 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/759310
System and method of programming a memory cell Feb 4, 2013 Issued
Array ( [id] => 9128668 [patent_doc_number] => 08576624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'On chip dynamic read for non-volatile storage' [patent_app_type] => utility [patent_app_number] => 13/759700 [patent_app_country] => US [patent_app_date] => 2013-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 14620 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13759700 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/759700
On chip dynamic read for non-volatile storage Feb 4, 2013 Issued
Array ( [id] => 9287755 [patent_doc_number] => 08644095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Input-output line sense amplifier having adjustable output drive capability' [patent_app_type] => utility [patent_app_number] => 13/758610 [patent_app_country] => US [patent_app_date] => 2013-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4852 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13758610 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/758610
Input-output line sense amplifier having adjustable output drive capability Feb 3, 2013 Issued
Array ( [id] => 10865600 [patent_doc_number] => 08891317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-18 [patent_title] => 'Volatile memory with a decreased consumption' [patent_app_type] => utility [patent_app_number] => 13/758536 [patent_app_country] => US [patent_app_date] => 2013-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6048 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13758536 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/758536
Volatile memory with a decreased consumption Feb 3, 2013 Issued
Array ( [id] => 8949096 [patent_doc_number] => 20130194876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'BUILT-IN SELF-TEST CIRCUIT APPLIED TO HIGH SPEED I/O PORT' [patent_app_type] => utility [patent_app_number] => 13/756662 [patent_app_country] => US [patent_app_date] => 2013-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3652 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13756662 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/756662
Built-in self-test circuit applied to high speed I/O port Jan 31, 2013 Issued
Array ( [id] => 8840310 [patent_doc_number] => 20130135938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME' [patent_app_type] => utility [patent_app_number] => 13/750602 [patent_app_country] => US [patent_app_date] => 2013-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17821 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13750602 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/750602
Nonvolatile semiconductor memory device and method for driving same Jan 24, 2013 Issued
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