
Ly D. Pham
Examiner (ID: 15722)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827, 2818, 2713 |
| Total Applications | 2164 |
| Issued Applications | 2016 |
| Pending Applications | 83 |
| Abandoned Applications | 106 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11207639
[patent_doc_number] => 09437267
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-09-06
[patent_title] => 'Storage element and memory'
[patent_app_type] => utility
[patent_app_number] => 14/359488
[patent_app_country] => US
[patent_app_date] => 2012-11-19
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/359488 | Storage element and memory | Nov 18, 2012 | Issued |
Array
(
[id] => 9498327
[patent_doc_number] => 08737156
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-27
[patent_title] => 'Mapping between two buses using serial addressing bits'
[patent_app_type] => utility
[patent_app_number] => 13/656758
[patent_app_country] => US
[patent_app_date] => 2012-10-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/656758 | Mapping between two buses using serial addressing bits | Oct 21, 2012 | Issued |
Array
(
[id] => 8827605
[patent_doc_number] => 20130128650
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-23
[patent_title] => 'DATA-MASKED ANALOG AND DIGITAL READ FOR RESISTIVE MEMORIES'
[patent_app_type] => utility
[patent_app_number] => 13/657002
[patent_app_country] => US
[patent_app_date] => 2012-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/657002 | Data-masked analog and digital read for resistive memories | Oct 21, 2012 | Issued |
Array
(
[id] => 9434142
[patent_doc_number] => 20140112048
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[patent_kind] => A1
[patent_issue_date] => 2014-04-24
[patent_title] => 'N-BIT ROM CELL'
[patent_app_type] => utility
[patent_app_number] => 13/655556
[patent_app_country] => US
[patent_app_date] => 2012-10-19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/655556 | N-bit rom cell | Oct 18, 2012 | Issued |
Array
(
[id] => 8670013
[patent_doc_number] => 20130044551
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-21
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
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[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/656320 | Semiconductor memory device | Oct 18, 2012 | Issued |
Array
(
[id] => 9470731
[patent_doc_number] => 08724374
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-05-13
[patent_title] => 'Data-dependent pullup transistor supply and body bias voltage application for a static random access memory (SRAM) cell'
[patent_app_type] => utility
[patent_app_number] => 13/655160
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/655160 | Data-dependent pullup transistor supply and body bias voltage application for a static random access memory (SRAM) cell | Oct 17, 2012 | Issued |
Array
(
[id] => 10931205
[patent_doc_number] => 20140334226
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[patent_kind] => A1
[patent_issue_date] => 2014-11-13
[patent_title] => 'CIRCUIT FOR REVERSE BIASING INVERTERS FOR REDUCING THE POWER CONSUMPTION OF AN SRAM MEMORY'
[patent_app_type] => utility
[patent_app_number] => 14/356562
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/356562 | Circuit for reverse biasing inverters for reducing the power consumption of an SRAM memory | Oct 17, 2012 | Issued |
Array
(
[id] => 9308486
[patent_doc_number] => 20140047160
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[patent_issue_date] => 2014-02-13
[patent_title] => 'DATA WRITING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/653424
[patent_app_country] => US
[patent_app_date] => 2012-10-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/653424 | Data writing method, and memory controller and memory storage apparatus using the same | Oct 16, 2012 | Issued |
Array
(
[id] => 10899829
[patent_doc_number] => 08923058
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-30
[patent_title] => 'Nonvolatile memory device'
[patent_app_type] => utility
[patent_app_number] => 13/653798
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/653798 | Nonvolatile memory device | Oct 16, 2012 | Issued |
Array
(
[id] => 9591064
[patent_doc_number] => 08780617
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[patent_kind] => B2
[patent_issue_date] => 2014-07-15
[patent_title] => 'Semiconductor memory device and method of performing burn-in test on the same'
[patent_app_type] => utility
[patent_app_number] => 13/653782
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/653782 | Semiconductor memory device and method of performing burn-in test on the same | Oct 16, 2012 | Issued |
Array
(
[id] => 9470761
[patent_doc_number] => 08724404
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[patent_kind] => B2
[patent_issue_date] => 2014-05-13
[patent_title] => 'Memory, supply voltage generation circuit, and operation method of a supply voltage generation circuit used for a memory array'
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[patent_app_number] => 13/652422
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/652422 | Memory, supply voltage generation circuit, and operation method of a supply voltage generation circuit used for a memory array | Oct 14, 2012 | Issued |
Array
(
[id] => 9553841
[patent_doc_number] => 08760901
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[patent_title] => 'Semiconductor device having a control chip stacked with a controlled chip'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/350434 | Method of pinning domain walls in a nanowire magnetic memory device | Oct 7, 2012 | Issued |
Array
(
[id] => 8584652
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[patent_title] => 'STACKED DEVICE REMAPPING AND REPAIR'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/616704 | Stacked device remapping and repair | Sep 13, 2012 | Issued |
Array
(
[id] => 9628110
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[patent_issue_date] => 2014-08-05
[patent_title] => 'Device selection schemes in multi chip package NAND flash memory system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/611580 | Device selection schemes in multi chip package NAND flash memory system | Sep 11, 2012 | Issued |
Array
(
[id] => 8983481
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[patent_title] => 'MRAM diode array and access method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/611225 | MRAM diode array and access method | Sep 11, 2012 | Issued |
Array
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[id] => 8890171
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/611084 | Memory device | Sep 11, 2012 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/610448 | Reference cell circuit and method of producing a reference current | Sep 10, 2012 | Issued |