Search

Ly D. Pham

Examiner (ID: 15722)

Most Active Art Unit
2827
Art Unit(s)
2827, 2818, 2713
Total Applications
2164
Issued Applications
2016
Pending Applications
83
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11207639 [patent_doc_number] => 09437267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Storage element and memory' [patent_app_type] => utility [patent_app_number] => 14/359488 [patent_app_country] => US [patent_app_date] => 2012-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 14357 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14359488 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/359488
Storage element and memory Nov 18, 2012 Issued
Array ( [id] => 9498327 [patent_doc_number] => 08737156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-27 [patent_title] => 'Mapping between two buses using serial addressing bits' [patent_app_type] => utility [patent_app_number] => 13/656758 [patent_app_country] => US [patent_app_date] => 2012-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 2362 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13656758 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/656758
Mapping between two buses using serial addressing bits Oct 21, 2012 Issued
Array ( [id] => 8827605 [patent_doc_number] => 20130128650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'DATA-MASKED ANALOG AND DIGITAL READ FOR RESISTIVE MEMORIES' [patent_app_type] => utility [patent_app_number] => 13/657002 [patent_app_country] => US [patent_app_date] => 2012-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5850 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13657002 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/657002
Data-masked analog and digital read for resistive memories Oct 21, 2012 Issued
Array ( [id] => 9434142 [patent_doc_number] => 20140112048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'N-BIT ROM CELL' [patent_app_type] => utility [patent_app_number] => 13/655556 [patent_app_country] => US [patent_app_date] => 2012-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13655556 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/655556
N-bit rom cell Oct 18, 2012 Issued
Array ( [id] => 8670013 [patent_doc_number] => 20130044551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/656320 [patent_app_country] => US [patent_app_date] => 2012-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7074 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13656320 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/656320
Semiconductor memory device Oct 18, 2012 Issued
Array ( [id] => 9470731 [patent_doc_number] => 08724374 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-13 [patent_title] => 'Data-dependent pullup transistor supply and body bias voltage application for a static random access memory (SRAM) cell' [patent_app_type] => utility [patent_app_number] => 13/655160 [patent_app_country] => US [patent_app_date] => 2012-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 8780 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13655160 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/655160
Data-dependent pullup transistor supply and body bias voltage application for a static random access memory (SRAM) cell Oct 17, 2012 Issued
Array ( [id] => 10931205 [patent_doc_number] => 20140334226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'CIRCUIT FOR REVERSE BIASING INVERTERS FOR REDUCING THE POWER CONSUMPTION OF AN SRAM MEMORY' [patent_app_type] => utility [patent_app_number] => 14/356562 [patent_app_country] => US [patent_app_date] => 2012-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6157 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14356562 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/356562
Circuit for reverse biasing inverters for reducing the power consumption of an SRAM memory Oct 17, 2012 Issued
Array ( [id] => 9308486 [patent_doc_number] => 20140047160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'DATA WRITING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/653424 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8538 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13653424 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/653424
Data writing method, and memory controller and memory storage apparatus using the same Oct 16, 2012 Issued
Array ( [id] => 10899829 [patent_doc_number] => 08923058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'Nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 13/653798 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9636 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13653798 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/653798
Nonvolatile memory device Oct 16, 2012 Issued
Array ( [id] => 9591064 [patent_doc_number] => 08780617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Semiconductor memory device and method of performing burn-in test on the same' [patent_app_type] => utility [patent_app_number] => 13/653782 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 10122 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13653782 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/653782
Semiconductor memory device and method of performing burn-in test on the same Oct 16, 2012 Issued
Array ( [id] => 9470761 [patent_doc_number] => 08724404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Memory, supply voltage generation circuit, and operation method of a supply voltage generation circuit used for a memory array' [patent_app_type] => utility [patent_app_number] => 13/652422 [patent_app_country] => US [patent_app_date] => 2012-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4988 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13652422 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/652422
Memory, supply voltage generation circuit, and operation method of a supply voltage generation circuit used for a memory array Oct 14, 2012 Issued
Array ( [id] => 9553841 [patent_doc_number] => 08760901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Semiconductor device having a control chip stacked with a controlled chip' [patent_app_type] => utility [patent_app_number] => 13/652030 [patent_app_country] => US [patent_app_date] => 2012-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 10657 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13652030 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/652030
Semiconductor device having a control chip stacked with a controlled chip Oct 14, 2012 Issued
Array ( [id] => 10570008 [patent_doc_number] => 09293184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-22 [patent_title] => 'Method of pinning domain walls in a nanowire magnetic memory device' [patent_app_type] => utility [patent_app_number] => 14/350434 [patent_app_country] => US [patent_app_date] => 2012-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3458 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14350434 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/350434
Method of pinning domain walls in a nanowire magnetic memory device Oct 7, 2012 Issued
Array ( [id] => 8584652 [patent_doc_number] => 20130003473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'STACKED DEVICE REMAPPING AND REPAIR' [patent_app_type] => utility [patent_app_number] => 13/616704 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8061 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13616704 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/616704
Stacked device remapping and repair Sep 13, 2012 Issued
Array ( [id] => 9628110 [patent_doc_number] => 08797799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Device selection schemes in multi chip package NAND flash memory system' [patent_app_type] => utility [patent_app_number] => 13/611580 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 7701 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13611580 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/611580
Device selection schemes in multi chip package NAND flash memory system Sep 11, 2012 Issued
Array ( [id] => 8983481 [patent_doc_number] => 08514605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'MRAM diode array and access method' [patent_app_type] => utility [patent_app_number] => 13/611225 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13611225 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/611225
MRAM diode array and access method Sep 11, 2012 Issued
Array ( [id] => 8890171 [patent_doc_number] => 20130163355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/611084 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13611084 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/611084
Memory device Sep 11, 2012 Issued
Array ( [id] => 9470730 [patent_doc_number] => 08724373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Apparatus for selective word-line boost on a memory cell' [patent_app_type] => utility [patent_app_number] => 13/609520 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5871 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13609520 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/609520
Apparatus for selective word-line boost on a memory cell Sep 10, 2012 Issued
Array ( [id] => 9351370 [patent_doc_number] => 08670269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-11 [patent_title] => 'Resistive memory device and method of writing data using multi-mode switching current' [patent_app_type] => utility [patent_app_number] => 13/609330 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 5387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13609330 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/609330
Resistive memory device and method of writing data using multi-mode switching current Sep 10, 2012 Issued
Array ( [id] => 9361893 [patent_doc_number] => 20140071766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'REFERENCE CELL CIRCUIT AND METHOD OF PRODUCING A REFERENCE CURRENT' [patent_app_type] => utility [patent_app_number] => 13/610448 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4272 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610448 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/610448
Reference cell circuit and method of producing a reference current Sep 10, 2012 Issued
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