Search

Ly D. Pham

Examiner (ID: 15722)

Most Active Art Unit
2827
Art Unit(s)
2827, 2818, 2713
Total Applications
2164
Issued Applications
2016
Pending Applications
83
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18789026 [patent_doc_number] => 20230377634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SEMICONDUCTOR ELEMENT MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/225572 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 401 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225572 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225572
Semiconductor element memory device Jul 23, 2023 Issued
Array ( [id] => 18789007 [patent_doc_number] => 20230377614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SERIES OF PARALLEL SENSING OPERATIONS FOR MULTI-LEVEL CELLS [patent_app_type] => utility [patent_app_number] => 18/357769 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357769 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357769
Series of parallel sensing operations for multi-level cells Jul 23, 2023 Issued
Array ( [id] => 20345824 [patent_doc_number] => 12469559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Non-volatile memory with sub-blocks [patent_app_type] => utility [patent_app_number] => 18/357450 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 30 [patent_no_of_words] => 11983 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357450 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357450
Non-volatile memory with sub-blocks Jul 23, 2023 Issued
Array ( [id] => 19964645 [patent_doc_number] => 12334160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Apparatus and method for detecting neighbor plane erase failures [patent_app_type] => utility [patent_app_number] => 18/355348 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 8307 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355348 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355348
Apparatus and method for detecting neighbor plane erase failures Jul 18, 2023 Issued
Array ( [id] => 19964645 [patent_doc_number] => 12334160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Apparatus and method for detecting neighbor plane erase failures [patent_app_type] => utility [patent_app_number] => 18/355348 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 8307 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355348 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355348
Apparatus and method for detecting neighbor plane erase failures Jul 18, 2023 Issued
Array ( [id] => 19964645 [patent_doc_number] => 12334160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Apparatus and method for detecting neighbor plane erase failures [patent_app_type] => utility [patent_app_number] => 18/355348 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 8307 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355348 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355348
Apparatus and method for detecting neighbor plane erase failures Jul 18, 2023 Issued
Array ( [id] => 18898334 [patent_doc_number] => 20240013819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => FLEXIBLE METADATA ALLOCATION AND CACHING [patent_app_type] => utility [patent_app_number] => 18/348716 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348716 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348716
Flexible metadata allocation and caching Jul 6, 2023 Issued
Array ( [id] => 19204806 [patent_doc_number] => 20240176705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SYSTEM RECOVERY DURING CGI-WL DEFECT [patent_app_type] => utility [patent_app_number] => 18/349093 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349093 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/349093
System recovery during CGI-WL defect Jul 6, 2023 Issued
Array ( [id] => 19392480 [patent_doc_number] => 20240282350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => SEMICONDUCTOR DEVICES PROVIDING TEST MODE RELATED TO RELIABILITY [patent_app_type] => utility [patent_app_number] => 18/342517 [patent_app_country] => US [patent_app_date] => 2023-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18342517 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/342517
SEMICONDUCTOR DEVICES PROVIDING TEST MODE RELATED TO RELIABILITY Jun 26, 2023 Pending
Array ( [id] => 19943443 [patent_doc_number] => 12315579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Memory device including sense amplifying circuit [patent_app_type] => utility [patent_app_number] => 18/333756 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 5765 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333756 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333756
Memory device including sense amplifying circuit Jun 12, 2023 Issued
Array ( [id] => 19951061 [patent_doc_number] => 12322431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Refresh address generation circuit and method, memory, and electronic device [patent_app_type] => utility [patent_app_number] => 18/332706 [patent_app_country] => US [patent_app_date] => 2023-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332706 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/332706
Refresh address generation circuit and method, memory, and electronic device Jun 8, 2023 Issued
Array ( [id] => 18898348 [patent_doc_number] => 20240013833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => SYSTEMS AND TECHNIQUES FOR ACCESSING MULTIPLE MEMORY CELLS CONCURRENTLY [patent_app_type] => utility [patent_app_number] => 18/208103 [patent_app_country] => US [patent_app_date] => 2023-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21803 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18208103 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/208103
Systems and techniques for accessing multiple memory cells concurrently Jun 8, 2023 Issued
Array ( [id] => 18820777 [patent_doc_number] => 20230395118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => ROW HAMMER MITIGATION [patent_app_type] => utility [patent_app_number] => 18/206241 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206241 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206241
Row hammer mitigation Jun 5, 2023 Issued
Array ( [id] => 19444240 [patent_doc_number] => 12094526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Memory device comprising electrically floating body transistor [patent_app_type] => utility [patent_app_number] => 18/205530 [patent_app_country] => US [patent_app_date] => 2023-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 66 [patent_no_of_words] => 19772 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18205530 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/205530
Memory device comprising electrically floating body transistor Jun 2, 2023 Issued
Array ( [id] => 19979991 [patent_doc_number] => 12347477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Integrated circuit memory devices having efficient row hammer management and memory systems including the same [patent_app_type] => utility [patent_app_number] => 18/327335 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 33 [patent_no_of_words] => 11163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327335
Integrated circuit memory devices having efficient row hammer management and memory systems including the same May 31, 2023 Issued
Array ( [id] => 19979991 [patent_doc_number] => 12347477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Integrated circuit memory devices having efficient row hammer management and memory systems including the same [patent_app_type] => utility [patent_app_number] => 18/327335 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 33 [patent_no_of_words] => 11163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327335
Integrated circuit memory devices having efficient row hammer management and memory systems including the same May 31, 2023 Issued
Array ( [id] => 19979991 [patent_doc_number] => 12347477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Integrated circuit memory devices having efficient row hammer management and memory systems including the same [patent_app_type] => utility [patent_app_number] => 18/327335 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 33 [patent_no_of_words] => 11163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327335
Integrated circuit memory devices having efficient row hammer management and memory systems including the same May 31, 2023 Issued
Array ( [id] => 19979991 [patent_doc_number] => 12347477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Integrated circuit memory devices having efficient row hammer management and memory systems including the same [patent_app_type] => utility [patent_app_number] => 18/327335 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 33 [patent_no_of_words] => 11163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327335
Integrated circuit memory devices having efficient row hammer management and memory systems including the same May 31, 2023 Issued
Array ( [id] => 19413321 [patent_doc_number] => 12079137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Banked memory architecture for multiple parallel datapath channels in an accelerator [patent_app_type] => utility [patent_app_number] => 18/203527 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11234 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203527 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/203527
Banked memory architecture for multiple parallel datapath channels in an accelerator May 29, 2023 Issued
Array ( [id] => 19531506 [patent_doc_number] => 20240355408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => CONTENT ADDRESSABLE MEMORY AND CONTENT ADDRESSABLE MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/323430 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323430 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323430
Content addressable memory and content addressable memory cell May 24, 2023 Issued
Menu