Search

Ly D. Pham

Examiner (ID: 490, Phone: (571)272-1793 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2713, 2818, 2827
Total Applications
2205
Issued Applications
2049
Pending Applications
85
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19244349 [patent_doc_number] => 12014800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Low standby power with fast turn on method for non-volatile memory devices [patent_app_type] => utility [patent_app_number] => 18/108762 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18108762 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/108762
Low standby power with fast turn on method for non-volatile memory devices Feb 12, 2023 Issued
Array ( [id] => 19305233 [patent_doc_number] => 20240233813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => DUMMY DATA-BASED READ REFERENCE VOLTAGE SEARCH OF NAND MEMORY [patent_app_type] => utility [patent_app_number] => 18/162742 [patent_app_country] => US [patent_app_date] => 2023-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18162742 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/162742
Dummy data-based read reference voltage search of NAND memory Jan 31, 2023 Issued
Array ( [id] => 19639498 [patent_doc_number] => 12170111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Nonvolatile memory device including selection transistors and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/103496 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 10235 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103496 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103496
Nonvolatile memory device including selection transistors and operating method thereof Jan 30, 2023 Issued
Array ( [id] => 19093697 [patent_doc_number] => 11955161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Command-triggered data clock distribution mode [patent_app_type] => utility [patent_app_number] => 18/103386 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8165 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103386 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103386
Command-triggered data clock distribution mode Jan 29, 2023 Issued
Array ( [id] => 19347169 [patent_doc_number] => 20240256132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => REMAPPING BAD BLOCKS IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/103183 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103183 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103183
Remapping bad blocks in a memory sub-system Jan 29, 2023 Issued
Array ( [id] => 18615521 [patent_doc_number] => 20230282258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => FINITE TIME COUNTING PERIOD COUNTING OF INFINITE DATA STREAMS [patent_app_type] => utility [patent_app_number] => 18/160292 [patent_app_country] => US [patent_app_date] => 2023-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18160292 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/160292
Finite time counting period counting of infinite data streams Jan 25, 2023 Issued
Array ( [id] => 19016068 [patent_doc_number] => 11923008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Ternary content addressable memory and decision generation method for the same [patent_app_type] => utility [patent_app_number] => 18/155827 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 7037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155827 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155827
Ternary content addressable memory and decision generation method for the same Jan 17, 2023 Issued
Array ( [id] => 19101662 [patent_doc_number] => 20240120890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => SENSING AND AMPLIFYING CIRCUIT RELATED TO A SENSING MARGIN [patent_app_type] => utility [patent_app_number] => 18/098576 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18098576 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/098576
SENSING AND AMPLIFYING CIRCUIT RELATED TO A SENSING MARGIN Jan 17, 2023 Pending
Array ( [id] => 18378160 [patent_doc_number] => 20230153247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => MEMORY DEVICES SUPPORTING READ/MODIFY/WRITE MEMORY OPERATIONS INVOLVING BOTH VOLATILE MEMORY AND NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/096034 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096034 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096034
MEMORY DEVICES SUPPORTING READ/MODIFY/WRITE MEMORY OPERATIONS INVOLVING BOTH VOLATILE MEMORY AND NONVOLATILE MEMORY Jan 11, 2023 Abandoned
Array ( [id] => 19842518 [patent_doc_number] => 12254917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Power supply circuit, memory, testing device, memory system, and electronic device [patent_app_type] => utility [patent_app_number] => 18/090065 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 11495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090065 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090065
Power supply circuit, memory, testing device, memory system, and electronic device Dec 27, 2022 Issued
Array ( [id] => 19679070 [patent_doc_number] => 12190941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Memory cell and memory device thereof [patent_app_type] => utility [patent_app_number] => 18/147015 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4083 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18147015 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/147015
Memory cell and memory device thereof Dec 27, 2022 Issued
Array ( [id] => 18472681 [patent_doc_number] => 20230206969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => BUFFER CONFIGURATIONS FOR COMMUNICATIONS BETWEEN MEMORY DIES AND A HOST DEVICE [patent_app_type] => utility [patent_app_number] => 18/086991 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18086991 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/086991
Buffer configurations for communications between memory dies and a host device Dec 21, 2022 Issued
Array ( [id] => 18873471 [patent_doc_number] => 11861282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Integrated circuit fin structure manufacturing method [patent_app_type] => utility [patent_app_number] => 18/065275 [patent_app_country] => US [patent_app_date] => 2022-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 17258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18065275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/065275
Integrated circuit fin structure manufacturing method Dec 12, 2022 Issued
Array ( [id] => 19596794 [patent_doc_number] => 12154647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Method and device for correcting errors in resistive memories [patent_app_type] => utility [patent_app_number] => 18/077122 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7218 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077122 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077122
Method and device for correcting errors in resistive memories Dec 6, 2022 Issued
Array ( [id] => 19459942 [patent_doc_number] => 12100443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Semiconductor-element-including memory device [patent_app_type] => utility [patent_app_number] => 18/076175 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 43 [patent_no_of_words] => 14579 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 608 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18076175 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/076175
Semiconductor-element-including memory device Dec 5, 2022 Issued
Array ( [id] => 18287177 [patent_doc_number] => 20230102649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => SEMICONDUCTOR DEVICE WITH SECURE ACCESS KEY AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/075272 [patent_app_country] => US [patent_app_date] => 2022-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18075272 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/075272
Semiconductor device with secure access key and associated methods and systems Dec 4, 2022 Issued
Array ( [id] => 19796040 [patent_doc_number] => 12237005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Nonvolatile memory devices that support enhanced power saving during standby modes [patent_app_type] => utility [patent_app_number] => 18/059574 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8036 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18059574 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/059574
Nonvolatile memory devices that support enhanced power saving during standby modes Nov 28, 2022 Issued
Array ( [id] => 19329387 [patent_doc_number] => 12047082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Semiconductor device including delay compensation circuit [patent_app_type] => utility [patent_app_number] => 17/994296 [patent_app_country] => US [patent_app_date] => 2022-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994296 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/994296
Semiconductor device including delay compensation circuit Nov 25, 2022 Issued
Array ( [id] => 18712548 [patent_doc_number] => 20230335181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => SEMICONDUCTOR MEMORY DEVICES AND ELECTRONIC DEVICES INCLUDING THE SEMICONDUCTOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/964092 [patent_app_country] => US [patent_app_date] => 2022-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17964092 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/964092
Semiconductor memory devices and electronic devices including the semiconductor memory devices Oct 11, 2022 Issued
Array ( [id] => 18326639 [patent_doc_number] => 20230124767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => TECHNIQUES FOR REDUCING DRAM POWER USAGE IN PERFORMING READ AND WRITE OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/959586 [patent_app_country] => US [patent_app_date] => 2022-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17959586 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/959586
Techniques for reducing DRAM power usage in performing read and write operations Oct 3, 2022 Issued
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