Lydia E. Edwards

Array ( [id] => 3775523 [patent_doc_number] => 05742761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Apparatus for adapting message protocols for a switch network and a bus' [patent_app_type] => 1 [patent_app_number] => 8/800070 [patent_app_country] => US [patent_app_date] => 1997-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 35 [patent_no_of_words] => 22695 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742761.pdf [firstpage_image] =>[orig_patent_app_number] => 800070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3761404 [patent_doc_number] => 05717946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Data processor' [patent_app_type] => 1 [patent_app_number] => 8/783531 [patent_app_country] => US [patent_app_date] => 1997-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 100 [patent_figures_cnt] => 104 [patent_no_of_words] => 42605 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717946.pdf [firstpage_image] =>[orig_patent_app_number] => 783531 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3852949 [patent_doc_number] => 05761691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Linearly addressable microprocessor cache' [patent_app_type] => 1 [patent_app_number] => 8/780263 [patent_app_country] => US [patent_app_date] => 1997-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9098 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761691.pdf [firstpage_image] =>[orig_patent_app_number] => 780263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3670758 [patent_doc_number] => 05659763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Apparatus and method for reducing power consumption by peripheral devices by controlling the interconnection of power supplies' [patent_app_type] => 1 [patent_app_number] => 8/751275 [patent_app_country] => US [patent_app_date] => 1996-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2438 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659763.pdf [firstpage_image] =>[orig_patent_app_number] => 751275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3860867 [patent_doc_number] => 05745884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'System and method for billing data grade network use on a per connection basis' [patent_app_type] => 1 [patent_app_number] => 8/733942 [patent_app_country] => US [patent_app_date] => 1996-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6926 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745884.pdf [firstpage_image] =>[orig_patent_app_number] => 733942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3900405 [patent_doc_number] => 05806049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Data processing system for global assessment of investment opportunity and cost' [patent_app_type] => 1 [patent_app_number] => 8/893579 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3899 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/806/05806049.pdf [firstpage_image] =>[orig_patent_app_number] => 893579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3804075 [patent_doc_number] => 05737628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Multiprocessor computer system with interleaved processing element nodes' [patent_app_type] => 1 [patent_app_number] => 8/662868 [patent_app_country] => US [patent_app_date] => 1996-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11499 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737628.pdf [firstpage_image] =>[orig_patent_app_number] => 662868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3677133 [patent_doc_number] => 05598575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Multiprocessor data memory sharing system in which access to the data memory is determined by the control processor\'s access to the program memory' [patent_app_type] => 1 [patent_app_number] => 8/626911 [patent_app_country] => US [patent_app_date] => 1996-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10410 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598575.pdf [firstpage_image] =>[orig_patent_app_number] => 626911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3893622 [patent_doc_number] => 05764910 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method and apparatus for encoding and using network resource locators' [patent_app_type] => 1 [patent_app_number] => 8/626601 [patent_app_country] => US [patent_app_date] => 1996-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6429 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764910.pdf [firstpage_image] =>[orig_patent_app_number] => 626601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3893622 [patent_doc_number] => 05764910 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method and apparatus for encoding and using network resource locators' [patent_app_type] => 1 [patent_app_number] => 8/626601 [patent_app_country] => US [patent_app_date] => 1996-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6429 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764910.pdf [firstpage_image] =>[orig_patent_app_number] => 626601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3922757 [patent_doc_number] => 05752259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache' [patent_app_type] => 1 [patent_app_number] => 8/621960 [patent_app_country] => US [patent_app_date] => 1996-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12439 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/752/05752259.pdf [firstpage_image] =>[orig_patent_app_number] => 621960 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3898028 [patent_doc_number] => 05748900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Adaptive congestion control mechanism for modular computer networks' [patent_app_type] => 1 [patent_app_number] => 8/615700 [patent_app_country] => US [patent_app_date] => 1996-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5035 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748900.pdf [firstpage_image] =>[orig_patent_app_number] => 615700 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3887740 [patent_doc_number] => 05838942 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Panic trap system and method' [patent_app_type] => 1 [patent_app_number] => 8/609807 [patent_app_country] => US [patent_app_date] => 1996-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10624 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838942.pdf [firstpage_image] =>[orig_patent_app_number] => 609807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3673089 [patent_doc_number] => 05592671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Resource management system and method' [patent_app_type] => 1 [patent_app_number] => 8/583484 [patent_app_country] => US [patent_app_date] => 1996-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4312 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592671.pdf [firstpage_image] =>[orig_patent_app_number] => 583484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3812449 [patent_doc_number] => 05781801 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Method and apparatus for receive buffer management in multi-sender communication systems' [patent_app_type] => 1 [patent_app_number] => 8/580011 [patent_app_country] => US [patent_app_date] => 1995-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 5004 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781801.pdf [firstpage_image] =>[orig_patent_app_number] => 580011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3671127 [patent_doc_number] => 05659789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Stopclock toggle system for powering two CPUs from a regulator only sized for one CPU' [patent_app_type] => 1 [patent_app_number] => 8/573963 [patent_app_country] => US [patent_app_date] => 1995-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 15240 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659789.pdf [firstpage_image] =>[orig_patent_app_number] => 573963 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3893283 [patent_doc_number] => 05729688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Network element managing system' [patent_app_type] => 1 [patent_app_number] => 8/448361 [patent_app_country] => US [patent_app_date] => 1995-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 12434 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729688.pdf [firstpage_image] =>[orig_patent_app_number] => 448361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3873096 [patent_doc_number] => 05768608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Data processing apparatus and method for making same' [patent_app_type] => 1 [patent_app_number] => 8/561760 [patent_app_country] => US [patent_app_date] => 1995-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 121 [patent_no_of_words] => 14629 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768608.pdf [firstpage_image] =>[orig_patent_app_number] => 561760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3808801 [patent_doc_number] => 05727227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Interrupt coprocessor configured to process interrupts in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/559659 [patent_app_country] => US [patent_app_date] => 1995-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8179 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/727/05727227.pdf [firstpage_image] =>[orig_patent_app_number] => 559659 [rel_patent_id] =>[rel_patent_doc_number] =>)