Search

Lydia E. Edwards

Examiner (ID: 12519, Phone: (571)270-3242 , Office: P/1799 )

Most Active Art Unit
1796
Art Unit(s)
1797, 1799, 1709, 1743, 1796, 1775, 1774
Total Applications
865
Issued Applications
467
Pending Applications
90
Abandoned Applications
317

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3123060 [patent_doc_number] => 05408670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Performing arithmetic in parallel on composite operands with packed multi-bit components' [patent_app_type] => 1 [patent_app_number] => 7/993925 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9980 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/408/05408670.pdf [firstpage_image] =>[orig_patent_app_number] => 993925 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/993925
Performing arithmetic in parallel on composite operands with packed multi-bit components Dec 17, 1992 Issued
07/992439 SYSTEM FOR GENERATING LOCAL AREA NETWORK OPERATING STATISTICS BASED ON MONITORED NETWORK TRAFFIC AND METHOD THEREFOR Dec 16, 1992 Abandoned
07/989302 ACTIVITY MASKING WITH MASK CONTEXT OF SIMD PROCESSORS Dec 10, 1992 Abandoned
Array ( [id] => 3082759 [patent_doc_number] => 05361373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-01 [patent_title] => 'Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor' [patent_app_type] => 1 [patent_app_number] => 7/989236 [patent_app_country] => US [patent_app_date] => 1992-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5006 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/361/05361373.pdf [firstpage_image] =>[orig_patent_app_number] => 989236 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/989236
Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor Dec 10, 1992 Issued
07/981806 PIPELINED DATA ORDERING SYSTEM Nov 24, 1992 Abandoned
Array ( [id] => 3139082 [patent_doc_number] => 05437044 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'Virtual operating unit for microprocessor-controlled devices' [patent_app_type] => 1 [patent_app_number] => 7/979914 [patent_app_country] => US [patent_app_date] => 1992-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2645 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/437/05437044.pdf [firstpage_image] =>[orig_patent_app_number] => 979914 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/979914
Virtual operating unit for microprocessor-controlled devices Nov 22, 1992 Issued
Array ( [id] => 3548914 [patent_doc_number] => 05495582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'System and method for interprocessor routing through an established communication session in a loosely coupled computer complex' [patent_app_type] => 1 [patent_app_number] => 7/978217 [patent_app_country] => US [patent_app_date] => 1992-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2820 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495582.pdf [firstpage_image] =>[orig_patent_app_number] => 978217 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/978217
System and method for interprocessor routing through an established communication session in a loosely coupled computer complex Nov 17, 1992 Issued
Array ( [id] => 3111757 [patent_doc_number] => 05319793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-07 [patent_title] => 'Method and apparatus for improved compression and recording of color video data in a personal computer using a plurality of lookup tables' [patent_app_type] => 1 [patent_app_number] => 7/964675 [patent_app_country] => US [patent_app_date] => 1992-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5862 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 837 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/319/05319793.pdf [firstpage_image] =>[orig_patent_app_number] => 964675 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/964675
Method and apparatus for improved compression and recording of color video data in a personal computer using a plurality of lookup tables Oct 20, 1992 Issued
07/938056 DATA STORAGE SUBSYSTEM HAVING DEDICATED LINKS CONNECTING A HOST ADAPTER, CONTROLLER AND DIRECT ACCESS STROAGE DEVICES Oct 18, 1992 Abandoned
07/962764 APPARATUS AND METHOD FOR GATHERING AND ENTERING DATA AND REQUIREMENTS FROM MULTIPLE USERS IN THE BUILDING OF PROCESS MODELS AND DATA MODELS Oct 18, 1992 Abandoned
Array ( [id] => 3841917 [patent_doc_number] => 05784604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Method and system for reduced run-time delay during conditional branch execution in pipelined processor systems utilizing selectively delayed sequential instruction purging' [patent_app_type] => 1 [patent_app_number] => 7/959183 [patent_app_country] => US [patent_app_date] => 1992-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5441 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784604.pdf [firstpage_image] =>[orig_patent_app_number] => 959183 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/959183
Method and system for reduced run-time delay during conditional branch execution in pipelined processor systems utilizing selectively delayed sequential instruction purging Oct 8, 1992 Issued
Array ( [id] => 3702187 [patent_doc_number] => 05604911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Method of and apparatus for preconditioning of a coefficient matrix of simultaneous linear equations' [patent_app_type] => 1 [patent_app_number] => 7/947801 [patent_app_country] => US [patent_app_date] => 1992-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7572 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604911.pdf [firstpage_image] =>[orig_patent_app_number] => 947801 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/947801
Method of and apparatus for preconditioning of a coefficient matrix of simultaneous linear equations Sep 20, 1992 Issued
Array ( [id] => 3784043 [patent_doc_number] => 05734826 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Variable cyclic redundancy coding method and apparatus for use in a multistage network' [patent_app_type] => 1 [patent_app_number] => 7/946513 [patent_app_country] => US [patent_app_date] => 1992-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 11343 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734826.pdf [firstpage_image] =>[orig_patent_app_number] => 946513 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/946513
Variable cyclic redundancy coding method and apparatus for use in a multistage network Sep 16, 1992 Issued
07/946506 APPARATUS FOR ADAPTING MESSAGE PROTOCOLS FOR A SWITCH NETWORK AND A BUS Sep 16, 1992 Abandoned
Array ( [id] => 3539938 [patent_doc_number] => 05542048 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Increasing probability multi-stage network' [patent_app_type] => 1 [patent_app_number] => 7/946514 [patent_app_country] => US [patent_app_date] => 1992-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 13207 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 484 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/542/05542048.pdf [firstpage_image] =>[orig_patent_app_number] => 946514 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/946514
Increasing probability multi-stage network Sep 16, 1992 Issued
07/938371 RAPID INSTRUCTION (PRE)FETCHING AND DISPATCHING USING PRIOR (PRE)FETCH PREDICTIVE ANNOTATIONS Aug 30, 1992 Abandoned
07/925984 METHOD AND APPARATUS FOR GENERATING A STATUS WORD IN A PIPELINED PROCESSOR Aug 4, 1992 Abandoned
Array ( [id] => 3017116 [patent_doc_number] => 05375250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-20 [patent_title] => 'Method of intelligent computing and neural-like processing of time and space functions' [patent_app_type] => 1 [patent_app_number] => 7/912899 [patent_app_country] => US [patent_app_date] => 1992-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9520 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 1357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/375/05375250.pdf [firstpage_image] =>[orig_patent_app_number] => 912899 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/912899
Method of intelligent computing and neural-like processing of time and space functions Jul 12, 1992 Issued
07/903299 APPARATUS AND METHOD FOR PROVIDING MULTIPLE OUTPUT SIGNALS FROM A SINGLE PROGRAMMING LINE GROUP Jun 23, 1992 Abandoned
07/902668 A QUANTUM DOT-TUNNEL DEVICE WHICH CAN BE SELECTIVELY EXCITED BY A FIRST LIGHT EMITTED SOURCE AND THE INFFORMATION THUS STORED CAN BE READ WITH A SECOND LIGHT EMITTING SOURCE Jun 21, 1992 Abandoned
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