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Lydia E. Edwards

Examiner (ID: 12519, Phone: (571)270-3242 , Office: P/1799 )

Most Active Art Unit
1796
Art Unit(s)
1797, 1799, 1709, 1743, 1796, 1775, 1774
Total Applications
865
Issued Applications
467
Pending Applications
90
Abandoned Applications
317
Applications
StatisticsSubscription-Only

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3627035 [patent_doc_number] => 05535405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Microsequencer bus controller system' [patent_app_type] => 1 [patent_app_number] => 8/172657 [patent_app_country] => US [patent_app_date] => 1993-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 39 [patent_no_of_words] => 15096 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535405.pdf [firstpage_image] =>[orig_patent_app_number] => 172657 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/172657 		Microsequencer bus controller system Dec 22, 1993 Issued
08/143640 A MULTIPROCESSOR DATA MEMORY SHARING SYSTEM IN WHICH ACCESS TO THE DATA MEMORY IS DETERMINED BY THE CONTROL PROCESSOR'S ACCESS TO THE PROGRAM MEMORY Oct 31, 1993 Abandoned
08/146381 LINEARLY ADDRESSABLE MICROPROCESSOR CACHE Oct 28, 1993 Abandoned
Array ( [id] => 3576907 [patent_doc_number] => 05483659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Apparatus for controlling a signal processing system to operate in high and low speed modes' [patent_app_type] => 1 [patent_app_number] => 8/137213 [patent_app_country] => US [patent_app_date] => 1993-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3379 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/483/05483659.pdf [firstpage_image] =>[orig_patent_app_number] => 137213 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/137213 		Apparatus for controlling a signal processing system to operate in high and low speed modes Oct 17, 1993 Issued
Array ( [id] => 3445297 [patent_doc_number] => 05378067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Network interface apparatus and method for reducing conflicts through the use of times' [patent_app_type] => 1 [patent_app_number] => 8/126682 [patent_app_country] => US [patent_app_date] => 1993-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3782 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/378/05378067.pdf [firstpage_image] =>[orig_patent_app_number] => 126682 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/126682 		Network interface apparatus and method for reducing conflicts through the use of times Sep 23, 1993 Issued
Array ( [id] => 3602814 [patent_doc_number] => 05488714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-30 [patent_title] => 'Computer program analyzer for adapting computer programs to different architectures' [patent_app_type] => 1 [patent_app_number] => 8/112631 [patent_app_country] => US [patent_app_date] => 1993-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10176 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/488/05488714.pdf [firstpage_image] =>[orig_patent_app_number] => 112631 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/112631 		Computer program analyzer for adapting computer programs to different architectures Aug 24, 1993 Issued
08/102011 MICROPROCESSOR-BASED FPGA Aug 2, 1993 Abandoned
08/090811 COMPUTER-BASED SYSTEM HAVING IMPROVED INFORMATION DISPLAY AND ACCESS FACILITIES Jul 11, 1993 Pending
08/088546 SHARED COMMAND LIST Jul 5, 1993 Pending
08/082971 HIGH SPEED LADDER INSTRUCTION PROCESS SYSTEM FOR A PROGRAMMABLE LOGIC CONTROLLER Jun 28, 1993 Pending
08/084085 BUS INTERFACE STRUCTURE AND SYSTEM FOR CONTROLLING THE BUS INTERFACE STRUCTURE Jun 27, 1993 Pending
08/081186 MICROCOMPUTER HAVING INSTRUCTION DECODER WHERE DECODING FUNCTION IS REWRITABLE Jun 24, 1993 Pending
08/082291 DATA PIPELINE SYSTEM AND DATA ENCODING METHOD Jun 23, 1993 Pending
08/080861 MINI-CACHE OPERATIONAL MODULE FOR ENHANCEMENT TO GENERAL CACHE Jun 21, 1993 Pending
Array ( [id] => 3852529 [patent_doc_number] => 05761664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Hierarchical data model for design automation' [patent_app_type] => 1 [patent_app_number] => 8/075241 [patent_app_country] => US [patent_app_date] => 1993-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7718 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761664.pdf [firstpage_image] =>[orig_patent_app_number] => 075241 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/075241 		Hierarchical data model for design automation Jun 10, 1993 Issued
Array ( [id] => 3123129 [patent_doc_number] => 05465369 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'Network structure for parallel software processing' [patent_app_type] => 1 [patent_app_number] => 8/075556 [patent_app_country] => US [patent_app_date] => 1993-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2814 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 967 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/465/05465369.pdf [firstpage_image] =>[orig_patent_app_number] => 075556 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/075556 		Network structure for parallel software processing Jun 9, 1993 Issued
08/072801 PARALLEL DATA PROCESSING DEVICE HAVING A CONCATENATED DATA PATH BETWEEN ELEMENTARY PROCESSORS Jun 6, 1993 Pending
08/070706 METHODS AND TEST PLATFORMS FOR PARALLEL HARDWARE/SOFTWARE DEVELOPMENT OF AN APPLICATION-SPECIFIC INTEGRATED CIRCUIT May 26, 1993 Pending
08/062252 FILE ACCESS SCHEME IN DISTRIBUTED DATA PROCESSING SYSTEM May 16, 1993 Pending
08/050802 DYNAMIC GLOBAL PORTFOLIO ALLOCATION SYSTEM Apr 20, 1993 Pending
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