Search

Lynette F. Smith

Examiner (ID: 7547)

Most Active Art Unit
1813
Art Unit(s)
1648, 1661, 1645, 1806, 1813, 1649
Total Applications
356
Issued Applications
174
Pending Applications
30
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17622021 [patent_doc_number] => 11341077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Method for the assignment of addresses by a master unit to a number of slave units [patent_app_type] => utility [patent_app_number] => 16/321483 [patent_app_country] => US [patent_app_date] => 2017-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1494 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16321483 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/321483
Method for the assignment of addresses by a master unit to a number of slave units Jul 31, 2017 Issued
Array ( [id] => 13845555 [patent_doc_number] => 20190026262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => SYSTEMS AND METHODS FOR RENDERING DATA BASED ON FIXED-LENGTH TEMPLATING [patent_app_type] => utility [patent_app_number] => 15/657062 [patent_app_country] => US [patent_app_date] => 2017-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15657062 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/657062
Systems and methods for rendering data based on fixed-length templating Jul 20, 2017 Issued
Array ( [id] => 16934803 [patent_doc_number] => 20210200692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SIGNAL COMBINER [patent_app_type] => utility [patent_app_number] => 16/077910 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16077910 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/077910
SIGNAL COMBINER Jun 19, 2017 Abandoned
Array ( [id] => 12025854 [patent_doc_number] => 20170315953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'MEMORY SYSTEM WITH INDEPENDENTLY ADJUSTABLE CORE AND INTERFACE DATA RATES' [patent_app_type] => utility [patent_app_number] => 15/626038 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9184 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15626038 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/626038
Memory system with independently adjustable core and interface data rates Jun 15, 2017 Issued
Array ( [id] => 13611105 [patent_doc_number] => 20180357102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => System and Method for Allocating Memory Devices Among Information Handling Systems in a Chassis [patent_app_type] => utility [patent_app_number] => 15/620592 [patent_app_country] => US [patent_app_date] => 2017-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4593 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15620592 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/620592
System and method for allocating memory devices among information handling systems in a chassis Jun 11, 2017 Issued
Array ( [id] => 13595513 [patent_doc_number] => 20180349305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => TECHNIQUES FOR ISSUING INTERRUPTS IN A DATA PROCESSING SYSTEM WITH MULTIPLE SCOPES [patent_app_type] => utility [patent_app_number] => 15/615338 [patent_app_country] => US [patent_app_date] => 2017-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15615338 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/615338
Techniques for issuing interrupts in a data processing system with multiple scopes Jun 5, 2017 Issued
Array ( [id] => 13595505 [patent_doc_number] => 20180349301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => NAND Flash Reset Control [patent_app_type] => utility [patent_app_number] => 15/610815 [patent_app_country] => US [patent_app_date] => 2017-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15610815 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/610815
NAND flash reset control May 31, 2017 Issued
Array ( [id] => 15048269 [patent_doc_number] => 20190335139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => TRANSMISSION DEVICE, RECEPTION DEVICE, CABLE, TRANSMISSION METHOD, AND RECEPTION METHOD [patent_app_type] => utility [patent_app_number] => 16/303167 [patent_app_country] => US [patent_app_date] => 2017-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16303167 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/303167
Transmission device, reception device, cable, transmission method, and reception method May 29, 2017 Issued
Array ( [id] => 13541087 [patent_doc_number] => 20180322090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => SYSTEMS AND METHODS FOR MULTI-ARCHITECTURE COMPUTING [patent_app_type] => utility [patent_app_number] => 15/584343 [patent_app_country] => US [patent_app_date] => 2017-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15584343 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/584343
Systems and methods for multi-architecture computing May 1, 2017 Issued
Array ( [id] => 15578367 [patent_doc_number] => 10579566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Point of sale device with switchable internal connection roles [patent_app_type] => utility [patent_app_number] => 15/582174 [patent_app_country] => US [patent_app_date] => 2017-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9023 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15582174 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/582174
Point of sale device with switchable internal connection roles Apr 27, 2017 Issued
Array ( [id] => 13692987 [patent_doc_number] => 20170357448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => SELECTIVE I/O PRIORITIZATION BY SYSTEM PROCESS/THREAD [patent_app_type] => utility [patent_app_number] => 15/496588 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15496588 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/496588
SELECTIVE I/O PRIORITIZATION BY SYSTEM PROCESS/THREAD Apr 24, 2017 Abandoned
Array ( [id] => 16217321 [patent_doc_number] => 10733135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Universal serial bus network switch [patent_app_type] => utility [patent_app_number] => 15/477792 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6977 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477792 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477792
Universal serial bus network switch Apr 2, 2017 Issued
Array ( [id] => 13467419 [patent_doc_number] => 20180285252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => OPTIMIZED MEMORY ACCESS BANDWIDTH DEVICES, SYSTEMS, AND METHODS FOR PROCESSING LOW SPATIAL LOCALITY DATA [patent_app_type] => utility [patent_app_number] => 15/477072 [patent_app_country] => US [patent_app_date] => 2017-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477072 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477072
OPTIMIZED MEMORY ACCESS BANDWIDTH DEVICES, SYSTEMS, AND METHODS FOR PROCESSING LOW SPATIAL LOCALITY DATA Mar 31, 2017 Abandoned
Array ( [id] => 13448681 [patent_doc_number] => 20180275883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => APPARATUSES AND METHODS FOR IN-MEMORY DATA SWITCHING NETWORKS [patent_app_type] => utility [patent_app_number] => 15/465340 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15465340 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/465340
Apparatuses and methods for in-memory data switching networks Mar 20, 2017 Issued
Array ( [id] => 13432763 [patent_doc_number] => 20180267924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => N-DEPTH ASYNCHRONOUS FIFO INCLUDING A COLLECTION OF 1-DEPTH FIFO CELLS [patent_app_type] => utility [patent_app_number] => 15/463985 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463985 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463985
N-depth asynchronous FIFO including a collection of 1-depth FIFO cells Mar 19, 2017 Issued
Array ( [id] => 14457823 [patent_doc_number] => 10324873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Hardware accelerated communications over a chip-to-chip interface [patent_app_type] => utility [patent_app_number] => 15/454441 [patent_app_country] => US [patent_app_date] => 2017-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10785 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15454441 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/454441
Hardware accelerated communications over a chip-to-chip interface Mar 8, 2017 Issued
Array ( [id] => 13417629 [patent_doc_number] => 20180260357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => I2C CLOCK STRETCH OVER I3C BUS [patent_app_type] => utility [patent_app_number] => 15/453678 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453678 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/453678
I2C CLOCK STRETCH OVER I3C BUS Mar 7, 2017 Abandoned
Array ( [id] => 11945125 [patent_doc_number] => 20170249276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'INTEGRATED CIRCUIT SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/441925 [patent_app_country] => US [patent_app_date] => 2017-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15441925 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/441925
Integrated circuit system Feb 23, 2017 Issued
Array ( [id] => 13376385 [patent_doc_number] => 20180239734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => HOT-SWAPPABLE PROTOCOL EXPANDER MODULE FOR STORAGE ARRAY [patent_app_type] => utility [patent_app_number] => 15/439024 [patent_app_country] => US [patent_app_date] => 2017-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15439024 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/439024
Hot-swappable protocol expander module for storage array Feb 21, 2017 Issued
Array ( [id] => 15578339 [patent_doc_number] => 10579552 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-03 [patent_title] => Interface architecture for master-to-master and slave-to-master communication [patent_app_type] => utility [patent_app_number] => 15/429018 [patent_app_country] => US [patent_app_date] => 2017-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15429018 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/429018
Interface architecture for master-to-master and slave-to-master communication Feb 8, 2017 Issued
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