Lynne Ann Gurley
Supervisory Patent Examiner (ID: 16126, Phone: (571)272-1670 , Office: P/2811 )
Most Active Art Unit | 2812 |
Art Unit(s) | 2812, 2899, 2811, 1104, 1763, 2814 |
Total Applications | 970 |
Issued Applications | 787 |
Pending Applications | 29 |
Abandoned Applications | 154 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 13808345
[patent_doc_number] => 10181441
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-15
[patent_title] => Through via structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 15/355988
[patent_app_country] => US
[patent_app_date] => 2016-11-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/355988 | Through via structure and manufacturing method thereof | Nov 17, 2016 | Issued |
Array
(
[id] => 11904312
[patent_doc_number] => 09773753
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[patent_kind] => B1
[patent_issue_date] => 2017-09-26
[patent_title] => 'Semiconductor devices and methods of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 15/356400
[patent_app_country] => US
[patent_app_date] => 2016-11-18
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Array
(
[id] => 11840370
[patent_doc_number] => 20170222090
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-03
[patent_title] => 'PROTECTIVE CAPPING LAYER FOR SPALLED GALLIUM NITRIDE'
[patent_app_type] => utility
[patent_app_number] => 15/353283
[patent_app_country] => US
[patent_app_date] => 2016-11-16
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/353283 | Protective capping layer for spalled gallium nitride | Nov 15, 2016 | Issued |
Array
(
[id] => 13819999
[patent_doc_number] => 10186779
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-22
[patent_title] => Semiconductor device package and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 15/348854
[patent_app_country] => US
[patent_app_date] => 2016-11-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/348854 | Semiconductor device package and method of manufacturing the same | Nov 9, 2016 | Issued |
Array
(
[id] => 12953695
[patent_doc_number] => 09837376
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[patent_kind] => B2
[patent_issue_date] => 2017-12-05
[patent_title] => Manufacturing method of semiconductor device and semiconductor device thereof
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[patent_app_number] => 15/346507
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/346507 | Manufacturing method of semiconductor device and semiconductor device thereof | Nov 7, 2016 | Issued |
Array
(
[id] => 11459947
[patent_doc_number] => 20170053853
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-23
[patent_title] => 'HEAT SPREADER WITH FLEXIBLE TOLERANCE MECHANISM'
[patent_app_type] => utility
[patent_app_number] => 15/345778
[patent_app_country] => US
[patent_app_date] => 2016-11-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/345778 | Heat spreader with flexible tolerance mechanism | Nov 7, 2016 | Issued |
Array
(
[id] => 11459943
[patent_doc_number] => 20170053849
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-23
[patent_title] => 'Thermal Dissipation Through Seal Rings in 3DIC Structure'
[patent_app_type] => utility
[patent_app_number] => 15/344838
[patent_app_country] => US
[patent_app_date] => 2016-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/344838 | Thermal dissipation through seal rings in 3DIC structure | Nov 6, 2016 | Issued |
Array
(
[id] => 11592820
[patent_doc_number] => 20170117231
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-27
[patent_title] => 'WIRE BOND WIRES FOR INTERFERENCE SHIELDING'
[patent_app_type] => utility
[patent_app_number] => 15/344990
[patent_app_country] => US
[patent_app_date] => 2016-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/344990 | Wire bond wires for interference shielding | Nov 6, 2016 | Issued |
Array
(
[id] => 12396198
[patent_doc_number] => 09966321
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-08
[patent_title] => Methods and apparatus for package with interposers
[patent_app_type] => utility
[patent_app_number] => 15/335260
[patent_app_country] => US
[patent_app_date] => 2016-10-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/335260 | Methods and apparatus for package with interposers | Oct 25, 2016 | Issued |
Array
(
[id] => 11608031
[patent_doc_number] => 20170125334
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-04
[patent_title] => 'PACKAGING ARRANGEMENTS INCLUDING HIGH DENSITY INTERCONNECT BRIDGE'
[patent_app_type] => utility
[patent_app_number] => 15/334188
[patent_app_country] => US
[patent_app_date] => 2016-10-25
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[patent_drawing_sheets_cnt] => 4
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/334188 | Packaging arrangements including high density interconnect bridge | Oct 24, 2016 | Issued |
Array
(
[id] => 12109002
[patent_doc_number] => 09865490
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-09
[patent_title] => 'Cyclic olefin polymer compositions and polysiloxane release layers for use in temporary wafer bonding processes'
[patent_app_type] => utility
[patent_app_number] => 15/332581
[patent_app_country] => US
[patent_app_date] => 2016-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/332581 | Cyclic olefin polymer compositions and polysiloxane release layers for use in temporary wafer bonding processes | Oct 23, 2016 | Issued |
Array
(
[id] => 14985139
[patent_doc_number] => 10446490
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-15
[patent_title] => Junctionless back end of the line via contact
[patent_app_type] => utility
[patent_app_number] => 15/292789
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/292789 | Junctionless back end of the line via contact | Oct 12, 2016 | Issued |
Array
(
[id] => 16202005
[patent_doc_number] => 10727185
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-28
[patent_title] => Multi-chip package with high density interconnects
[patent_app_type] => utility
[patent_app_number] => 16/329644
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[rel_patent_id] =>[rel_patent_doc_number] =>) 16/329644 | Multi-chip package with high density interconnects | Sep 29, 2016 | Issued |
Array
(
[id] => 12935932
[patent_doc_number] => 09831202
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-28
[patent_title] => Semiconductor devices with solder-based connection terminals and method of forming the same
[patent_app_type] => utility
[patent_app_number] => 15/262040
[patent_app_country] => US
[patent_app_date] => 2016-09-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/262040 | Semiconductor devices with solder-based connection terminals and method of forming the same | Sep 11, 2016 | Issued |
Array
(
[id] => 12243290
[patent_doc_number] => 20180076153
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-15
[patent_title] => 'POWER MODULE ASSEMBLY WITH REDUCED INDUCTANCE'
[patent_app_type] => utility
[patent_app_number] => 15/260858
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[patent_app_date] => 2016-09-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/260858 | Power module assembly with reduced inductance | Sep 8, 2016 | Issued |
Array
(
[id] => 12355002
[patent_doc_number] => 09953846
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[patent_issue_date] => 2018-04-24
[patent_title] => Method for fabricating a semiconductor chip panel
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/261354 | Method for fabricating a semiconductor chip panel | Sep 8, 2016 | Issued |
Array
(
[id] => 11551636
[patent_doc_number] => 09620494
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-11
[patent_title] => 'Hybrid substrates, semiconductor packages including the same and methods for fabricating semiconductor packages'
[patent_app_type] => utility
[patent_app_number] => 15/260723
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/260723 | Hybrid substrates, semiconductor packages including the same and methods for fabricating semiconductor packages | Sep 8, 2016 | Issued |
Array
(
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[patent_issue_date] => 2018-01-11
[patent_title] => 'INTERCONNECT STRUCTURE FORMED WITH A HIGH ASPECT RATIO SINGLE DAMASCENE COPPER LINE ON A NON-DAMASCENE VIA'
[patent_app_type] => utility
[patent_app_number] => 15/261644
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/261644 | Interconnect structure formed with a high aspect ratio single damascene copper line on a non-damascene via | Sep 8, 2016 | Issued |
Array
(
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[patent_issue_date] => 2017-08-22
[patent_title] => 'Redistribution layers in semiconductor packages and methods of forming same'
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Array
(
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