Search

Lynne Ann Gurley

Supervisory Patent Examiner (ID: 16126, Phone: (571)272-1670 , Office: P/2811 )

Most Active Art Unit
2812
Art Unit(s)
2812, 2899, 2811, 1104, 1763, 2814
Total Applications
970
Issued Applications
787
Pending Applications
29
Abandoned Applications
154

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11898160 [patent_doc_number] => 09768101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'High density integrated circuit package structure and integrated circuit' [patent_app_type] => utility [patent_app_number] => 15/260069 [patent_app_country] => US [patent_app_date] => 2016-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 5057 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15260069 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/260069
High density integrated circuit package structure and integrated circuit Sep 7, 2016 Issued
Array ( [id] => 14151659 [patent_doc_number] => 10256219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Forming embedded circuit elements in semiconductor package assembles and structures formed thereby [patent_app_type] => utility [patent_app_number] => 15/260138 [patent_app_country] => US [patent_app_date] => 2016-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 6909 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15260138 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/260138
Forming embedded circuit elements in semiconductor package assembles and structures formed thereby Sep 7, 2016 Issued
Array ( [id] => 12236117 [patent_doc_number] => 20180068980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'MULTIPLE INTERCONNECTIONS BETWEEN DIE' [patent_app_type] => utility [patent_app_number] => 15/259980 [patent_app_country] => US [patent_app_date] => 2016-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11699 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15259980 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/259980
Multiple interconnections between die Sep 7, 2016 Issued
Array ( [id] => 11847528 [patent_doc_number] => 09735086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Power semiconductor module having a two-part housing' [patent_app_type] => utility [patent_app_number] => 15/259496 [patent_app_country] => US [patent_app_date] => 2016-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3053 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15259496 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/259496
Power semiconductor module having a two-part housing Sep 7, 2016 Issued
Array ( [id] => 11459981 [patent_doc_number] => 20170053887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/255351 [patent_app_country] => US [patent_app_date] => 2016-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5194 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15255351 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/255351
High density substrate routing in BBUL package Sep 1, 2016 Issued
Array ( [id] => 12477933 [patent_doc_number] => 09991232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Package and packaging process of a semiconductor device [patent_app_type] => utility [patent_app_number] => 15/253823 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 4803 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15253823 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/253823
Package and packaging process of a semiconductor device Aug 30, 2016 Issued
Array ( [id] => 11592803 [patent_doc_number] => 20170117215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING FLEXIBLE INTERCONNECTION AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/252519 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4144 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15252519 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/252519
Semiconductor device having flexible interconnection and method for fabricating the same Aug 30, 2016 Issued
Array ( [id] => 11592803 [patent_doc_number] => 20170117215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING FLEXIBLE INTERCONNECTION AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/252519 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4144 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15252519 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/252519
Semiconductor device having flexible interconnection and method for fabricating the same Aug 30, 2016 Issued
Array ( [id] => 11592803 [patent_doc_number] => 20170117215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING FLEXIBLE INTERCONNECTION AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/252519 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4144 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15252519 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/252519
Semiconductor device having flexible interconnection and method for fabricating the same Aug 30, 2016 Issued
Array ( [id] => 11592803 [patent_doc_number] => 20170117215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING FLEXIBLE INTERCONNECTION AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/252519 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4144 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15252519 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/252519
Semiconductor device having flexible interconnection and method for fabricating the same Aug 30, 2016 Issued
Array ( [id] => 11432025 [patent_doc_number] => 09570349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Non-lithographically patterned directed self assembly alignment promotion layers' [patent_app_type] => utility [patent_app_number] => 15/237542 [patent_app_country] => US [patent_app_date] => 2016-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 13805 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15237542 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/237542
Non-lithographically patterned directed self assembly alignment promotion layers Aug 14, 2016 Issued
Array ( [id] => 11315444 [patent_doc_number] => 20160351554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'Package-on-Package Structures and Methods for Forming the Same' [patent_app_type] => utility [patent_app_number] => 15/231884 [patent_app_country] => US [patent_app_date] => 2016-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15231884 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/231884
Package-on-package structures and methods for forming the same Aug 8, 2016 Issued
Array ( [id] => 13145693 [patent_doc_number] => 10090185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/225228 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 41 [patent_no_of_words] => 12176 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225228 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/225228
Semiconductor device and manufacturing method thereof Jul 31, 2016 Issued
Array ( [id] => 14985205 [patent_doc_number] => 10446523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Semiconductor device and method of forming wire studs as vertical interconnect in FO-WLP [patent_app_type] => utility [patent_app_number] => 15/218847 [patent_app_country] => US [patent_app_date] => 2016-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 32 [patent_no_of_words] => 6595 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15218847 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/218847
Semiconductor device and method of forming wire studs as vertical interconnect in FO-WLP Jul 24, 2016 Issued
Array ( [id] => 11557712 [patent_doc_number] => 20170103958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/213505 [patent_app_country] => US [patent_app_date] => 2016-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15213505 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/213505
SEMICONDUCTOR PACKAGE Jul 18, 2016 Abandoned
Array ( [id] => 12141110 [patent_doc_number] => 20180019193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'BALL GRID ARRAY (BGA) WITH ANCHORING PINS' [patent_app_type] => utility [patent_app_number] => 15/212951 [patent_app_country] => US [patent_app_date] => 2016-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6353 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15212951 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/212951
Ball grid array (BGA) with anchoring pins Jul 17, 2016 Issued
Array ( [id] => 11117045 [patent_doc_number] => 20160314018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'METHOD FOR WORK SCHEDULING IN A MULTI-CHIP SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/200587 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 21842 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15200587 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/200587
Method for work scheduling in a multi-chip system Jun 30, 2016 Issued
Array ( [id] => 15015235 [patent_doc_number] => 10453776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/196153 [patent_app_country] => US [patent_app_date] => 2016-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 40 [patent_no_of_words] => 10502 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15196153 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/196153
Semiconductor device Jun 28, 2016 Issued
Array ( [id] => 11096619 [patent_doc_number] => 20160293588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'Process for Forming Package-on-Package Structures' [patent_app_type] => utility [patent_app_number] => 15/186757 [patent_app_country] => US [patent_app_date] => 2016-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 4489 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15186757 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/186757
Process for forming package-on-package structures Jun 19, 2016 Issued
Array ( [id] => 16218511 [patent_doc_number] => 10734333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Semiconductor package having inductive lateral interconnects [patent_app_type] => utility [patent_app_number] => 16/093828 [patent_app_country] => US [patent_app_date] => 2016-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16093828 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/093828
Semiconductor package having inductive lateral interconnects Jun 14, 2016 Issued
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