Lynne Ann Gurley
Supervisory Patent Examiner (ID: 16126, Phone: (571)272-1670 , Office: P/2811 )
Most Active Art Unit | 2812 |
Art Unit(s) | 2812, 2899, 2811, 1104, 1763, 2814 |
Total Applications | 970 |
Issued Applications | 787 |
Pending Applications | 29 |
Abandoned Applications | 154 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 11898160
[patent_doc_number] => 09768101
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-09-19
[patent_title] => 'High density integrated circuit package structure and integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 15/260069
[patent_app_country] => US
[patent_app_date] => 2016-09-08
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15260069
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Array
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[patent_doc_number] => 10256219
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[patent_kind] => B2
[patent_issue_date] => 2019-04-09
[patent_title] => Forming embedded circuit elements in semiconductor package assembles and structures formed thereby
[patent_app_type] => utility
[patent_app_number] => 15/260138
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[patent_app_date] => 2016-09-08
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Array
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[patent_kind] => A1
[patent_issue_date] => 2018-03-08
[patent_title] => 'MULTIPLE INTERCONNECTIONS BETWEEN DIE'
[patent_app_type] => utility
[patent_app_number] => 15/259980
[patent_app_country] => US
[patent_app_date] => 2016-09-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/259980 | Multiple interconnections between die | Sep 7, 2016 | Issued |
Array
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[id] => 11847528
[patent_doc_number] => 09735086
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[patent_kind] => B2
[patent_issue_date] => 2017-08-15
[patent_title] => 'Power semiconductor module having a two-part housing'
[patent_app_type] => utility
[patent_app_number] => 15/259496
[patent_app_country] => US
[patent_app_date] => 2016-09-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/259496 | Power semiconductor module having a two-part housing | Sep 7, 2016 | Issued |
Array
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[patent_kind] => A1
[patent_issue_date] => 2017-02-23
[patent_title] => 'HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/255351 | High density substrate routing in BBUL package | Sep 1, 2016 | Issued |
Array
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[id] => 12477933
[patent_doc_number] => 09991232
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[patent_kind] => B2
[patent_issue_date] => 2018-06-05
[patent_title] => Package and packaging process of a semiconductor device
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[patent_app_number] => 15/253823
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Array
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Array
(
[id] => 11432025
[patent_doc_number] => 09570349
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[patent_issue_date] => 2017-02-14
[patent_title] => 'Non-lithographically patterned directed self assembly alignment promotion layers'
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Array
(
[id] => 11315444
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[patent_title] => 'Package-on-Package Structures and Methods for Forming the Same'
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Array
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Array
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[id] => 14985205
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[patent_title] => Semiconductor device and method of forming wire studs as vertical interconnect in FO-WLP
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Array
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Array
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Array
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