Search

Lynne Ann Gurley

Supervisory Patent Examiner (ID: 16126, Phone: (571)272-1670 , Office: P/2811 )

Most Active Art Unit
2812
Art Unit(s)
2812, 2899, 2811, 1104, 1763, 2814
Total Applications
970
Issued Applications
787
Pending Applications
29
Abandoned Applications
154

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10195766 [patent_doc_number] => 09224680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'Electrical connections for chip scale packaging' [patent_app_type] => utility [patent_app_number] => 14/571068 [patent_app_country] => US [patent_app_date] => 2014-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14571068 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/571068
Electrical connections for chip scale packaging Dec 14, 2014 Issued
Array ( [id] => 10590604 [patent_doc_number] => 09312224 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-12 [patent_title] => 'Interconnect structure containing a porous low k interconnect dielectric/dielectric cap' [patent_app_type] => utility [patent_app_number] => 14/567537 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7346 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567537 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/567537
Interconnect structure containing a porous low k interconnect dielectric/dielectric cap Dec 10, 2014 Issued
Array ( [id] => 12416826 [patent_doc_number] => 09972557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Integrated circuit (IC) package with a solder receiving area and associated methods [patent_app_type] => utility [patent_app_number] => 14/567070 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3134 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567070 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/567070
Integrated circuit (IC) package with a solder receiving area and associated methods Dec 10, 2014 Issued
Array ( [id] => 10223645 [patent_doc_number] => 20150108638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'Package on Package Structure and Method of Manufacturing the Same' [patent_app_type] => utility [patent_app_number] => 14/557227 [patent_app_country] => US [patent_app_date] => 2014-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14557227 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/557227
Package on package structure and method of manufacturing the same Nov 30, 2014 Issued
Array ( [id] => 11431998 [patent_doc_number] => 09570322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Integrated circuit packages and methods of forming same' [patent_app_type] => utility [patent_app_number] => 14/555374 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 9604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14555374 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/555374
Integrated circuit packages and methods of forming same Nov 25, 2014 Issued
Array ( [id] => 9928492 [patent_doc_number] => 20150076684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 14/553835 [patent_app_country] => US [patent_app_date] => 2014-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14553835 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/553835
Semiconductor device Nov 24, 2014 Issued
Array ( [id] => 10151827 [patent_doc_number] => 09184124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Reliable surface mount integrated power module' [patent_app_type] => utility [patent_app_number] => 14/547667 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5553 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14547667 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/547667
Reliable surface mount integrated power module Nov 18, 2014 Issued
Array ( [id] => 11214721 [patent_doc_number] => 09443760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Multichip power semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/543557 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 7162 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14543557 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/543557
Multichip power semiconductor device Nov 16, 2014 Issued
Array ( [id] => 10245059 [patent_doc_number] => 20150130054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/538018 [patent_app_country] => US [patent_app_date] => 2014-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14538018 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/538018
SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Nov 10, 2014 Abandoned
Array ( [id] => 11207938 [patent_doc_number] => 09437570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Power converter package with an integrated output inductor' [patent_app_type] => utility [patent_app_number] => 14/538483 [patent_app_country] => US [patent_app_date] => 2014-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14538483 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/538483
Power converter package with an integrated output inductor Nov 10, 2014 Issued
Array ( [id] => 10518777 [patent_doc_number] => 09245831 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-01-26 [patent_title] => 'Top-exposed semiconductor package and the manufacturing method' [patent_app_type] => utility [patent_app_number] => 14/533244 [patent_app_country] => US [patent_app_date] => 2014-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1636 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14533244 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/533244
Top-exposed semiconductor package and the manufacturing method Nov 4, 2014 Issued
Array ( [id] => 10617675 [patent_doc_number] => 09337124 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-10 [patent_title] => 'Method of integration of wafer level heat spreaders and backside interconnects on microelectronics wafers' [patent_app_type] => utility [patent_app_number] => 14/532761 [patent_app_country] => US [patent_app_date] => 2014-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 5433 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14532761 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/532761
Method of integration of wafer level heat spreaders and backside interconnects on microelectronics wafers Nov 3, 2014 Issued
Array ( [id] => 10238295 [patent_doc_number] => 20150123290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'SEMICONDUCTOR PACKAGES HAVING TRENCH-SHAPED OPENING AND METHODS FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/531994 [patent_app_country] => US [patent_app_date] => 2014-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 9953 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14531994 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/531994
Semiconductor packages having trench-shaped opening and methods for fabricating the same Nov 2, 2014 Issued
Array ( [id] => 11411755 [patent_doc_number] => 09559068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Wafer scale package for high power devices' [patent_app_type] => utility [patent_app_number] => 14/520270 [patent_app_country] => US [patent_app_date] => 2014-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 5847 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14520270 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/520270
Wafer scale package for high power devices Oct 20, 2014 Issued
Array ( [id] => 10610975 [patent_doc_number] => 09331017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Chip package incorporating interfacial adhesion through conductor sputtering' [patent_app_type] => utility [patent_app_number] => 14/506357 [patent_app_country] => US [patent_app_date] => 2014-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4357 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14506357 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/506357
Chip package incorporating interfacial adhesion through conductor sputtering Oct 2, 2014 Issued
Array ( [id] => 11360196 [patent_doc_number] => 09536852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Lead frame having a perimeter recess within periphery of component terminal' [patent_app_type] => utility [patent_app_number] => 14/503646 [patent_app_country] => US [patent_app_date] => 2014-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5306 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14503646 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/503646
Lead frame having a perimeter recess within periphery of component terminal Sep 30, 2014 Issued
Array ( [id] => 10744143 [patent_doc_number] => 20160090294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'PACKAGE ARRANGEMENT, A PACKAGE, AND A METHOD OF MANUFACTURING A PACKAGE ARRANGEMENT' [patent_app_type] => utility [patent_app_number] => 14/495920 [patent_app_country] => US [patent_app_date] => 2014-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11402 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14495920 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/495920
Package arrangement, a package, and a method of manufacturing a package arrangement Sep 24, 2014 Issued
Array ( [id] => 9844079 [patent_doc_number] => 08945994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Single layer coreless substrate' [patent_app_type] => utility [patent_app_number] => 14/485948 [patent_app_country] => US [patent_app_date] => 2014-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 6413 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14485948 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/485948
Single layer coreless substrate Sep 14, 2014 Issued
Array ( [id] => 10394804 [patent_doc_number] => 20150279811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY' [patent_app_type] => utility [patent_app_number] => 14/477363 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5508 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477363 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/477363
Manufacturing method of semiconductor device and semiconductor device manufactured thereby Sep 3, 2014 Issued
Array ( [id] => 10370416 [patent_doc_number] => 20150255421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'SEMICONDUCTOR MANUFACTURING DEVICE AND SEMICONDUCTOR MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 14/475726 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6158 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475726 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/475726
Semiconductor manufacturing device and semiconductor manufacturing method Sep 2, 2014 Issued
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