Lynne Ann Gurley
Supervisory Patent Examiner (ID: 16126, Phone: (571)272-1670 , Office: P/2811 )
Most Active Art Unit | 2812 |
Art Unit(s) | 2812, 2899, 2811, 1104, 1763, 2814 |
Total Applications | 970 |
Issued Applications | 787 |
Pending Applications | 29 |
Abandoned Applications | 154 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 16132427
[patent_doc_number] => 10699981
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-30
[patent_title] => Non-vertical through-via in package
[patent_app_type] => utility
[patent_app_number] => 16/173210
[patent_app_country] => US
[patent_app_date] => 2018-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 5143
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16173210
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/173210 | Non-vertical through-via in package | Oct 28, 2018 | Issued |
Array
(
[id] => 14252639
[patent_doc_number] => 10276526
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-30
[patent_title] => Semiconductor package structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 16/162389
[patent_app_country] => US
[patent_app_date] => 2018-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 33
[patent_no_of_words] => 6465
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16162389
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/162389 | Semiconductor package structure and manufacturing method thereof | Oct 16, 2018 | Issued |
Array
(
[id] => 15315469
[patent_doc_number] => 10522450
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-12-31
[patent_title] => Pillar based socket
[patent_app_type] => utility
[patent_app_number] => 16/159861
[patent_app_country] => US
[patent_app_date] => 2018-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 8542
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16159861
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/159861 | Pillar based socket | Oct 14, 2018 | Issued |
Array
(
[id] => 15286413
[patent_doc_number] => 10515876
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-12-24
[patent_title] => Method for forming semiconductor device and semiconductor device fabricated by the same
[patent_app_type] => utility
[patent_app_number] => 16/159789
[patent_app_country] => US
[patent_app_date] => 2018-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 5100
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16159789
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/159789 | Method for forming semiconductor device and semiconductor device fabricated by the same | Oct 14, 2018 | Issued |
Array
(
[id] => 16293512
[patent_doc_number] => 10770367
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-08
[patent_title] => Semiconductor apparatus, method for manufacturing the same and electric power conversion device
[patent_app_type] => utility
[patent_app_number] => 16/159745
[patent_app_country] => US
[patent_app_date] => 2018-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4705
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16159745
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/159745 | Semiconductor apparatus, method for manufacturing the same and electric power conversion device | Oct 14, 2018 | Issued |
Array
(
[id] => 15375871
[patent_doc_number] => 10529663
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-01-07
[patent_title] => Copper interconnect with filled void
[patent_app_type] => utility
[patent_app_number] => 16/159671
[patent_app_country] => US
[patent_app_date] => 2018-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 6857
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16159671
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/159671 | Copper interconnect with filled void | Oct 13, 2018 | Issued |
Array
(
[id] => 16214945
[patent_doc_number] => 10730743
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-04
[patent_title] => Gas sensor packages
[patent_app_type] => utility
[patent_app_number] => 16/159477
[patent_app_country] => US
[patent_app_date] => 2018-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7712
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16159477
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/159477 | Gas sensor packages | Oct 11, 2018 | Issued |
Array
(
[id] => 16386540
[patent_doc_number] => 10811385
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-10-20
[patent_title] => Wafer-level system-in-package structure and electronic apparatus thereof
[patent_app_type] => utility
[patent_app_number] => 16/158789
[patent_app_country] => US
[patent_app_date] => 2018-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 22
[patent_no_of_words] => 10110
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16158789
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/158789 | Wafer-level system-in-package structure and electronic apparatus thereof | Oct 11, 2018 | Issued |
Array
(
[id] => 15234193
[patent_doc_number] => 10504826
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-12-10
[patent_title] => Device almost last embedded device structure and method of manufacturing thereof
[patent_app_type] => utility
[patent_app_number] => 16/153892
[patent_app_country] => US
[patent_app_date] => 2018-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 48
[patent_no_of_words] => 16911
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16153892
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/153892 | Device almost last embedded device structure and method of manufacturing thereof | Oct 7, 2018 | Issued |
Array
(
[id] => 16041343
[patent_doc_number] => 10682523
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-16
[patent_title] => Interconnect structure and method of forming same
[patent_app_type] => utility
[patent_app_number] => 16/154154
[patent_app_country] => US
[patent_app_date] => 2018-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 17
[patent_no_of_words] => 6531
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16154154
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/154154 | Interconnect structure and method of forming same | Oct 7, 2018 | Issued |
Array
(
[id] => 16067551
[patent_doc_number] => 10692737
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-23
[patent_title] => Multilayer interconnect structure with buried conductive via connections and method of manufacturing thereof
[patent_app_type] => utility
[patent_app_number] => 16/153905
[patent_app_country] => US
[patent_app_date] => 2018-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 48
[patent_no_of_words] => 16936
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16153905
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/153905 | Multilayer interconnect structure with buried conductive via connections and method of manufacturing thereof | Oct 7, 2018 | Issued |
Array
(
[id] => 15475363
[patent_doc_number] => 10553566
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-04
[patent_title] => Stacked semiconductor die assemblies with die substrate extensions
[patent_app_type] => utility
[patent_app_number] => 16/154659
[patent_app_country] => US
[patent_app_date] => 2018-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 4010
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16154659
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/154659 | Stacked semiconductor die assemblies with die substrate extensions | Oct 7, 2018 | Issued |
Array
(
[id] => 16521628
[patent_doc_number] => 10872853
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-22
[patent_title] => Module
[patent_app_type] => utility
[patent_app_number] => 16/152920
[patent_app_country] => US
[patent_app_date] => 2018-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4853
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16152920
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/152920 | Module | Oct 4, 2018 | Issued |
Array
(
[id] => 14938725
[patent_doc_number] => 20190305001
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-03
[patent_title] => DISPLAY PANEL AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/152646
[patent_app_country] => US
[patent_app_date] => 2018-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2071
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16152646
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/152646 | Display panel and display device | Oct 4, 2018 | Issued |
Array
(
[id] => 15611417
[patent_doc_number] => 10586778
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-10
[patent_title] => Elastic wave element and elastic wave apparatus
[patent_app_type] => utility
[patent_app_number] => 16/150354
[patent_app_country] => US
[patent_app_date] => 2018-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 8795
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 274
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16150354
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/150354 | Elastic wave element and elastic wave apparatus | Oct 2, 2018 | Issued |
Array
(
[id] => 14285259
[patent_doc_number] => 20190139914
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-09
[patent_title] => MICROWAVE IC WAVEGUIDE DEVICE MODULE
[patent_app_type] => utility
[patent_app_number] => 16/145491
[patent_app_country] => US
[patent_app_date] => 2018-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 45401
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -25
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145491
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/145491 | Microwave IC waveguide device module | Sep 27, 2018 | Issued |
Array
(
[id] => 13879257
[patent_doc_number] => 20190035969
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-31
[patent_title] => Nitride Underlayer and Fabrication Method Thereof
[patent_app_type] => utility
[patent_app_number] => 16/145127
[patent_app_country] => US
[patent_app_date] => 2018-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3651
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145127
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/145127 | Nitride underlayer and fabrication method thereof | Sep 26, 2018 | Issued |
Array
(
[id] => 15488351
[patent_doc_number] => 10559537
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-11
[patent_title] => Wire bond wires for interference shielding
[patent_app_type] => utility
[patent_app_number] => 16/127110
[patent_app_country] => US
[patent_app_date] => 2018-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 23
[patent_no_of_words] => 8538
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16127110
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/127110 | Wire bond wires for interference shielding | Sep 9, 2018 | Issued |
Array
(
[id] => 14955129
[patent_doc_number] => 10438843
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-10-08
[patent_title] => Semiconductor device and method for fabricating the same
[patent_app_type] => utility
[patent_app_number] => 16/119980
[patent_app_country] => US
[patent_app_date] => 2018-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 3461
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119980
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/119980 | Semiconductor device and method for fabricating the same | Aug 30, 2018 | Issued |
Array
(
[id] => 15170283
[patent_doc_number] => 10490647
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-11-26
[patent_title] => Method of forming metal silicide layer, semiconductor device and method of fabricating same
[patent_app_type] => utility
[patent_app_number] => 16/119277
[patent_app_country] => US
[patent_app_date] => 2018-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 6743
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119277
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/119277 | Method of forming metal silicide layer, semiconductor device and method of fabricating same | Aug 30, 2018 | Issued |