Search

Lynne Ann Gurley

Supervisory Patent Examiner (ID: 16126, Phone: (571)272-1670 , Office: P/2811 )

Most Active Art Unit
2812
Art Unit(s)
2812, 2899, 2811, 1104, 1763, 2814
Total Applications
970
Issued Applications
787
Pending Applications
29
Abandoned Applications
154

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14875421 [patent_doc_number] => 20190287952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/119624 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119624 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119624
Semiconductor device Aug 30, 2018 Issued
Array ( [id] => 15077869 [patent_doc_number] => 10468435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Display panel and display device including display panel [patent_app_type] => utility [patent_app_number] => 16/119994 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119994 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119994
Display panel and display device including display panel Aug 30, 2018 Issued
Array ( [id] => 14875367 [patent_doc_number] => 20190287925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/119945 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119945 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119945
Semiconductor device and manufacturing method thereof Aug 30, 2018 Issued
Array ( [id] => 15061453 [patent_doc_number] => 10461038 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-29 [patent_title] => Methods of alignment marking semiconductor wafers, and semiconductor packages having portions of alignment markings [patent_app_type] => utility [patent_app_number] => 16/118902 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 8265 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16118902 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/118902
Methods of alignment marking semiconductor wafers, and semiconductor packages having portions of alignment markings Aug 30, 2018 Issued
Array ( [id] => 15580703 [patent_doc_number] => 10580745 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-03 [patent_title] => Wafer level packaging with integrated antenna structures [patent_app_type] => utility [patent_app_number] => 16/118791 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 6942 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16118791 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/118791
Wafer level packaging with integrated antenna structures Aug 30, 2018 Issued
Array ( [id] => 15564511 [patent_doc_number] => 20200066667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE FOR JOINING WAFERS AND RESULTING STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/106239 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16106239 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/106239
Methods of forming integrated circuit structure for joining wafers and resulting structure Aug 20, 2018 Issued
Array ( [id] => 15580607 [patent_doc_number] => 10580696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-03 [patent_title] => Interconnects formed by a metal displacement reaction [patent_app_type] => utility [patent_app_number] => 16/106246 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16106246 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/106246
Interconnects formed by a metal displacement reaction Aug 20, 2018 Issued
Array ( [id] => 14525935 [patent_doc_number] => 10340238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Wiring substrate and semiconductor device [patent_app_type] => utility [patent_app_number] => 16/106236 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 14915 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16106236 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/106236
Wiring substrate and semiconductor device Aug 20, 2018 Issued
Array ( [id] => 15061911 [patent_doc_number] => 10461268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Flexible display panel and display device [patent_app_type] => utility [patent_app_number] => 16/105981 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 13471 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105981 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/105981
Flexible display panel and display device Aug 20, 2018 Issued
Array ( [id] => 13740701 [patent_doc_number] => 20180374820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 16/107677 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107677 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107677
Manufacturing method of semiconductor device and semiconductor device thereof Aug 20, 2018 Issued
Array ( [id] => 14366875 [patent_doc_number] => 10304750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Package structure and its fabrication method [patent_app_type] => utility [patent_app_number] => 16/106107 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3912 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16106107 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/106107
Package structure and its fabrication method Aug 20, 2018 Issued
Array ( [id] => 14024497 [patent_doc_number] => 20190074242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => LEAD FRAME AND METHOD OF MANUFACTURING LEAD FRAME [patent_app_type] => utility [patent_app_number] => 16/106460 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16106460 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/106460
Lead frame and method of manufacturing lead frame Aug 20, 2018 Issued
Array ( [id] => 14587733 [patent_doc_number] => 20190221475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/106266 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16106266 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/106266
Semiconductor device Aug 20, 2018 Issued
Array ( [id] => 14955245 [patent_doc_number] => 10438901 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-08 [patent_title] => Integrated circuit package comprising an enhanced electromagnetic shield [patent_app_type] => utility [patent_app_number] => 16/106117 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6307 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16106117 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/106117
Integrated circuit package comprising an enhanced electromagnetic shield Aug 20, 2018 Issued
Array ( [id] => 13799463 [patent_doc_number] => 20190013270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/103186 [patent_app_country] => US [patent_app_date] => 2018-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103186 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/103186
Semiconductor device and manufacturing method thereof Aug 13, 2018 Issued
Array ( [id] => 13571117 [patent_doc_number] => 20180337106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => BUMP-ON-TRACE PACKAGING STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/050669 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050669 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050669
Bump-on-trace packaging structure and method for forming the same Jul 30, 2018 Issued
Array ( [id] => 15315517 [patent_doc_number] => 10522474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Staircase etch control in forming three-dimensional memory device [patent_app_type] => utility [patent_app_number] => 16/046820 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 15729 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046820 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/046820
Staircase etch control in forming three-dimensional memory device Jul 25, 2018 Issued
Array ( [id] => 13571195 [patent_doc_number] => 20180337145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING DUMMY CONDUCTIVE CELLS [patent_app_type] => utility [patent_app_number] => 16/046449 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046449 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/046449
Semiconductor device including dummy conductive cells Jul 25, 2018 Issued
Array ( [id] => 13558873 [patent_doc_number] => 20180330984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => Packages with Through-Vias Having Tapered Ends [patent_app_type] => utility [patent_app_number] => 16/035910 [patent_app_country] => US [patent_app_date] => 2018-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035910 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/035910
Packages with through-vias having tapered ends Jul 15, 2018 Issued
Array ( [id] => 13543259 [patent_doc_number] => 20180323176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/036413 [patent_app_country] => US [patent_app_date] => 2018-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16036413 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/036413
Semiconductor apparatus and semiconductor system including the same Jul 15, 2018 Issued
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