Search

Mackly Monestime

Examiner (ID: 3491)

Most Active Art Unit
2676
Art Unit(s)
2671, 2676, 2783, 2674, 2183
Total Applications
304
Issued Applications
271
Pending Applications
18
Abandoned Applications
15

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4404284 [patent_doc_number] => 06263429 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Dynamic microcode for embedded processors' [patent_app_type] => 1 [patent_app_number] => 9/164256 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8149 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263429.pdf [firstpage_image] =>[orig_patent_app_number] => 164256 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/164256
Dynamic microcode for embedded processors Sep 29, 1998 Issued
Array ( [id] => 4375389 [patent_doc_number] => 06219684 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Optimized rounding in underflow handlers' [patent_app_type] => 1 [patent_app_number] => 9/164075 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3094 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219684.pdf [firstpage_image] =>[orig_patent_app_number] => 164075 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/164075
Optimized rounding in underflow handlers Sep 29, 1998 Issued
Array ( [id] => 4147741 [patent_doc_number] => 06128719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Indirect rotator graph network' [patent_app_type] => 1 [patent_app_number] => 9/157584 [patent_app_country] => US [patent_app_date] => 1998-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6725 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128719.pdf [firstpage_image] =>[orig_patent_app_number] => 157584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/157584
Indirect rotator graph network Sep 20, 1998 Issued
Array ( [id] => 4171719 [patent_doc_number] => 06125443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Interrupt processing system and method for information processing system of pipeline control type' [patent_app_type] => 1 [patent_app_number] => 9/154715 [patent_app_country] => US [patent_app_date] => 1998-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5143 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125443.pdf [firstpage_image] =>[orig_patent_app_number] => 154715 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154715
Interrupt processing system and method for information processing system of pipeline control type Sep 16, 1998 Issued
Array ( [id] => 4152830 [patent_doc_number] => 06148392 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Low power implementation of an asynchronous stock having a constant response time' [patent_app_type] => 1 [patent_app_number] => 9/148863 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4031 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148392.pdf [firstpage_image] =>[orig_patent_app_number] => 148863 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/148863
Low power implementation of an asynchronous stock having a constant response time Sep 7, 1998 Issued
Array ( [id] => 4167381 [patent_doc_number] => 06065107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'System for restoring register data in a pipelined data processing system using latch feedback assemblies' [patent_app_type] => 1 [patent_app_number] => 9/141925 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8179 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065107.pdf [firstpage_image] =>[orig_patent_app_number] => 141925 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/141925
System for restoring register data in a pipelined data processing system using latch feedback assemblies Aug 27, 1998 Issued
Array ( [id] => 4388947 [patent_doc_number] => 06275951 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Reset signal control circuit of a one-chip microcomputer' [patent_app_type] => 1 [patent_app_number] => 9/135687 [patent_app_country] => US [patent_app_date] => 1998-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3670 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275951.pdf [firstpage_image] =>[orig_patent_app_number] => 135687 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/135687
Reset signal control circuit of a one-chip microcomputer Aug 17, 1998 Issued
Array ( [id] => 1462455 [patent_doc_number] => 06427201 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Information processing apparatus for entertainment system utilizing DMA-controlled high-speed transfer and processing of routine data' [patent_app_type] => B1 [patent_app_number] => 09/135724 [patent_app_country] => US [patent_app_date] => 1998-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5190 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427201.pdf [firstpage_image] =>[orig_patent_app_number] => 09135724 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/135724
Information processing apparatus for entertainment system utilizing DMA-controlled high-speed transfer and processing of routine data Aug 17, 1998 Issued
Array ( [id] => 4426660 [patent_doc_number] => 06178497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'System and method for determining the relative age of instructions in a processor' [patent_app_type] => 1 [patent_app_number] => 9/134342 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3300 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178497.pdf [firstpage_image] =>[orig_patent_app_number] => 134342 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/134342
System and method for determining the relative age of instructions in a processor Aug 13, 1998 Issued
Array ( [id] => 4298309 [patent_doc_number] => 06282595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Method for testing interface card' [patent_app_type] => 1 [patent_app_number] => 9/128631 [patent_app_country] => US [patent_app_date] => 1998-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2896 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282595.pdf [firstpage_image] =>[orig_patent_app_number] => 128631 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/128631
Method for testing interface card Aug 3, 1998 Issued
Array ( [id] => 4391935 [patent_doc_number] => 06289438 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Microprocessor cache redundancy scheme using store buffer' [patent_app_type] => 1 [patent_app_number] => 9/127119 [patent_app_country] => US [patent_app_date] => 1998-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3767 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289438.pdf [firstpage_image] =>[orig_patent_app_number] => 127119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/127119
Microprocessor cache redundancy scheme using store buffer Jul 28, 1998 Issued
Array ( [id] => 4392465 [patent_doc_number] => 06289472 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method and test system for testing under a plurality of test modes' [patent_app_type] => 1 [patent_app_number] => 9/123699 [patent_app_country] => US [patent_app_date] => 1998-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4652 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289472.pdf [firstpage_image] =>[orig_patent_app_number] => 123699 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/123699
Method and test system for testing under a plurality of test modes Jul 27, 1998 Issued
Array ( [id] => 1557694 [patent_doc_number] => 06401217 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method for error recognition in a processor system' [patent_app_type] => B1 [patent_app_number] => 09/120786 [patent_app_country] => US [patent_app_date] => 1998-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6007 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401217.pdf [firstpage_image] =>[orig_patent_app_number] => 09120786 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/120786
Method for error recognition in a processor system Jul 21, 1998 Issued
Array ( [id] => 1526487 [patent_doc_number] => 06353880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Four stage pipeline processing for a microcontroller' [patent_app_type] => B1 [patent_app_number] => 09/121224 [patent_app_country] => US [patent_app_date] => 1998-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6031 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 452 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353880.pdf [firstpage_image] =>[orig_patent_app_number] => 09121224 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/121224
Four stage pipeline processing for a microcontroller Jul 21, 1998 Issued
Array ( [id] => 1466683 [patent_doc_number] => 06351799 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Integrated circuit for executing software programs' [patent_app_type] => B1 [patent_app_number] => 09/115170 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2567 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351799.pdf [firstpage_image] =>[orig_patent_app_number] => 09115170 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/115170
Integrated circuit for executing software programs Jul 13, 1998 Issued
Array ( [id] => 4340716 [patent_doc_number] => 06313766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Method and apparatus for accelerating software decode of variable length encoded information' [patent_app_type] => 1 [patent_app_number] => 9/109008 [patent_app_country] => US [patent_app_date] => 1998-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3748 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313766.pdf [firstpage_image] =>[orig_patent_app_number] => 109008 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/109008
Method and apparatus for accelerating software decode of variable length encoded information Jun 30, 1998 Issued
Array ( [id] => 4399458 [patent_doc_number] => 06295598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Split directory-based cache coherency technique for a multi-processor computer system' [patent_app_type] => 1 [patent_app_number] => 9/108088 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5536 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295598.pdf [firstpage_image] =>[orig_patent_app_number] => 108088 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/108088
Split directory-based cache coherency technique for a multi-processor computer system Jun 29, 1998 Issued
Array ( [id] => 4192247 [patent_doc_number] => 06141713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Bus arbitrator with a hierarchical control structure' [patent_app_type] => 1 [patent_app_number] => 9/104543 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2701 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141713.pdf [firstpage_image] =>[orig_patent_app_number] => 104543 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/104543
Bus arbitrator with a hierarchical control structure Jun 25, 1998 Issued
Array ( [id] => 4268842 [patent_doc_number] => 06138193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'System for reducing noise in bus having plurality of first and second set of signals and a delay device for delaying propagation of second signals' [patent_app_type] => 1 [patent_app_number] => 9/103356 [patent_app_country] => US [patent_app_date] => 1998-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2667 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138193.pdf [firstpage_image] =>[orig_patent_app_number] => 103356 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/103356
System for reducing noise in bus having plurality of first and second set of signals and a delay device for delaying propagation of second signals Jun 22, 1998 Issued
Array ( [id] => 4316179 [patent_doc_number] => 06199132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Communication link with isochronous and asynchronous priority modes' [patent_app_type] => 1 [patent_app_number] => 9/098854 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9199 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199132.pdf [firstpage_image] =>[orig_patent_app_number] => 098854 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098854
Communication link with isochronous and asynchronous priority modes Jun 16, 1998 Issued
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