Search

Mackly Monestime

Examiner (ID: 3491)

Most Active Art Unit
2676
Art Unit(s)
2671, 2676, 2783, 2674, 2183
Total Applications
304
Issued Applications
271
Pending Applications
18
Abandoned Applications
15

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4426876 [patent_doc_number] => 06195716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'System bus interface controlling at least one slave device by exchanging three control signals' [patent_app_type] => 1 [patent_app_number] => 9/095951 [patent_app_country] => US [patent_app_date] => 1998-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5399 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195716.pdf [firstpage_image] =>[orig_patent_app_number] => 095951 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095951
System bus interface controlling at least one slave device by exchanging three control signals Jun 10, 1998 Issued
Array ( [id] => 4206697 [patent_doc_number] => 06154683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Low voltage industrial control system providing intrinsically safe operation' [patent_app_type] => 1 [patent_app_number] => 9/090204 [patent_app_country] => US [patent_app_date] => 1998-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 6168 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154683.pdf [firstpage_image] =>[orig_patent_app_number] => 090204 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/090204
Low voltage industrial control system providing intrinsically safe operation Jun 2, 1998 Issued
Array ( [id] => 4422293 [patent_doc_number] => 06272585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Multiple interrupt handling method and apparatus' [patent_app_type] => 1 [patent_app_number] => 9/088232 [patent_app_country] => US [patent_app_date] => 1998-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2232 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272585.pdf [firstpage_image] =>[orig_patent_app_number] => 088232 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/088232
Multiple interrupt handling method and apparatus May 31, 1998 Issued
Array ( [id] => 4260144 [patent_doc_number] => 06092174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Dynamically reconfigurable distributed integrated circuit processor and method' [patent_app_type] => 1 [patent_app_number] => 9/088165 [patent_app_country] => US [patent_app_date] => 1998-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5754 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092174.pdf [firstpage_image] =>[orig_patent_app_number] => 088165 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/088165
Dynamically reconfigurable distributed integrated circuit processor and method May 31, 1998 Issued
Array ( [id] => 4260883 [patent_doc_number] => 06092223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Redundancy circuit for semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/084391 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3849 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092223.pdf [firstpage_image] =>[orig_patent_app_number] => 084391 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/084391
Redundancy circuit for semiconductor integrated circuit May 26, 1998 Issued
Array ( [id] => 4155556 [patent_doc_number] => 06122689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Bus termination circuitry and methods for implementing the same' [patent_app_type] => 1 [patent_app_number] => 9/078346 [patent_app_country] => US [patent_app_date] => 1998-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5268 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122689.pdf [firstpage_image] =>[orig_patent_app_number] => 078346 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/078346
Bus termination circuitry and methods for implementing the same May 12, 1998 Issued
Array ( [id] => 4310376 [patent_doc_number] => 06212619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'System and method for high-speed register renaming by counting' [patent_app_type] => 1 [patent_app_number] => 9/075918 [patent_app_country] => US [patent_app_date] => 1998-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 4939 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212619.pdf [firstpage_image] =>[orig_patent_app_number] => 075918 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/075918
System and method for high-speed register renaming by counting May 10, 1998 Issued
Array ( [id] => 4255281 [patent_doc_number] => 06119219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'System serialization with early release of individual processor' [patent_app_type] => 1 [patent_app_number] => 9/070595 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7995 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119219.pdf [firstpage_image] =>[orig_patent_app_number] => 070595 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/070595
System serialization with early release of individual processor Apr 29, 1998 Issued
Array ( [id] => 4224169 [patent_doc_number] => 06079013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Multiprocessor serialization with early release of processors' [patent_app_type] => 1 [patent_app_number] => 9/070429 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7999 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/079/06079013.pdf [firstpage_image] =>[orig_patent_app_number] => 070429 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/070429
Multiprocessor serialization with early release of processors Apr 29, 1998 Issued
Array ( [id] => 4178951 [patent_doc_number] => 06115777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'LOADRS instruction and asynchronous context switch' [patent_app_type] => 1 [patent_app_number] => 9/063739 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9794 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115777.pdf [firstpage_image] =>[orig_patent_app_number] => 063739 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063739
LOADRS instruction and asynchronous context switch Apr 20, 1998 Issued
Array ( [id] => 4237462 [patent_doc_number] => 06112292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Code sequence for asynchronous backing store switch utilizing both the cover and LOADRS instructions' [patent_app_type] => 1 [patent_app_number] => 9/064025 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9782 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112292.pdf [firstpage_image] =>[orig_patent_app_number] => 064025 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/064025
Code sequence for asynchronous backing store switch utilizing both the cover and LOADRS instructions Apr 20, 1998 Issued
09/034801 INTEGRATED FIXED AND PROGRAMMABLE FUNCTION DSP Mar 3, 1998 Abandoned
Array ( [id] => 4352042 [patent_doc_number] => 06314508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'RISC type microprocessor and information processing apparatus' [patent_app_type] => 1 [patent_app_number] => 9/027025 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 5845 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314508.pdf [firstpage_image] =>[orig_patent_app_number] => 027025 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/027025
RISC type microprocessor and information processing apparatus Feb 19, 1998 Issued
Array ( [id] => 4426649 [patent_doc_number] => 06178493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Multiprocessor stalled store detection' [patent_app_type] => 1 [patent_app_number] => 9/026088 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1634 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178493.pdf [firstpage_image] =>[orig_patent_app_number] => 026088 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026088
Multiprocessor stalled store detection Feb 18, 1998 Issued
Array ( [id] => 1443962 [patent_doc_number] => 06336180 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Method, apparatus and system for managing virtual memory with virtual-physical mapping' [patent_app_type] => B1 [patent_app_number] => 09/025755 [patent_app_country] => US [patent_app_date] => 1998-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 135 [patent_figures_cnt] => 167 [patent_no_of_words] => 69029 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/336/06336180.pdf [firstpage_image] =>[orig_patent_app_number] => 09025755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025755
Method, apparatus and system for managing virtual memory with virtual-physical mapping Feb 17, 1998 Issued
Array ( [id] => 4426623 [patent_doc_number] => 06178484 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'DCBST with ICBI mechanism to maintain coherency of bifurcated data and instruction caches' [patent_app_type] => 1 [patent_app_number] => 9/024585 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4819 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178484.pdf [firstpage_image] =>[orig_patent_app_number] => 024585 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024585
DCBST with ICBI mechanism to maintain coherency of bifurcated data and instruction caches Feb 16, 1998 Issued
Array ( [id] => 4123992 [patent_doc_number] => 06101582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Dcbst with icbi mechanism' [patent_app_type] => 1 [patent_app_number] => 9/024639 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4816 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101582.pdf [firstpage_image] =>[orig_patent_app_number] => 024639 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024639
Dcbst with icbi mechanism Feb 16, 1998 Issued
Array ( [id] => 4101136 [patent_doc_number] => 06163836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Processor with programmable addressing modes' [patent_app_type] => 1 [patent_app_number] => 9/022285 [patent_app_country] => US [patent_app_date] => 1998-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 9236 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163836.pdf [firstpage_image] =>[orig_patent_app_number] => 022285 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/022285
Processor with programmable addressing modes Feb 10, 1998 Issued
Array ( [id] => 4025894 [patent_doc_number] => 05941960 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Host initiated PCI burst writes utilizing posted write buffers' [patent_app_type] => 1 [patent_app_number] => 9/022302 [patent_app_country] => US [patent_app_date] => 1998-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2097 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941960.pdf [firstpage_image] =>[orig_patent_app_number] => 022302 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/022302
Host initiated PCI burst writes utilizing posted write buffers Feb 10, 1998 Issued
Array ( [id] => 4162600 [patent_doc_number] => 06032249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method and system for executing a serializing instruction while bypassing a floating point unit pipeline' [patent_app_type] => 1 [patent_app_number] => 9/016981 [patent_app_country] => US [patent_app_date] => 1998-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3129 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032249.pdf [firstpage_image] =>[orig_patent_app_number] => 016981 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/016981
Method and system for executing a serializing instruction while bypassing a floating point unit pipeline Feb 1, 1998 Issued
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