Search

Mackly Monestime

Examiner (ID: 3491)

Most Active Art Unit
2676
Art Unit(s)
2671, 2676, 2783, 2674, 2183
Total Applications
304
Issued Applications
271
Pending Applications
18
Abandoned Applications
15

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4237447 [patent_doc_number] => 06112291 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method and apparatus for performing a shift instruction with saturate by examination of an operand prior to shifting' [patent_app_type] => 1 [patent_app_number] => 9/012325 [patent_app_country] => US [patent_app_date] => 1998-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 4559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112291.pdf [firstpage_image] =>[orig_patent_app_number] => 012325 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/012325
Method and apparatus for performing a shift instruction with saturate by examination of an operand prior to shifting Jan 22, 1998 Issued
Array ( [id] => 4334881 [patent_doc_number] => 06243775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'System for extending the available number of configuration registers' [patent_app_type] => 1 [patent_app_number] => 9/008973 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2800 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243775.pdf [firstpage_image] =>[orig_patent_app_number] => 008973 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/008973
System for extending the available number of configuration registers Jan 19, 1998 Issued
Array ( [id] => 4333359 [patent_doc_number] => 06317823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Apparatus and method for processing information with recognizing a situation and medium storing program therefor' [patent_app_type] => 1 [patent_app_number] => 8/997791 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 42 [patent_no_of_words] => 9920 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317823.pdf [firstpage_image] =>[orig_patent_app_number] => 997791 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997791
Apparatus and method for processing information with recognizing a situation and medium storing program therefor Dec 23, 1997 Issued
Array ( [id] => 4057135 [patent_doc_number] => 05909574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Computing system with exception handler and method of handling exceptions in a computing system' [patent_app_type] => 1 [patent_app_number] => 8/996765 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5715 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909574.pdf [firstpage_image] =>[orig_patent_app_number] => 996765 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/996765
Computing system with exception handler and method of handling exceptions in a computing system Dec 22, 1997 Issued
Array ( [id] => 4176485 [patent_doc_number] => 06157974 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Hot plugging system which precharging data signal pins to the reference voltage that was generated from voltage detected on the operating mode signal conductor in the bus' [patent_app_type] => 1 [patent_app_number] => 8/996841 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3159 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157974.pdf [firstpage_image] =>[orig_patent_app_number] => 996841 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/996841
Hot plugging system which precharging data signal pins to the reference voltage that was generated from voltage detected on the operating mode signal conductor in the bus Dec 22, 1997 Issued
Array ( [id] => 3916076 [patent_doc_number] => 05951671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Sharing instruction predecode information in a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/993475 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8098 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951671.pdf [firstpage_image] =>[orig_patent_app_number] => 993475 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993475
Sharing instruction predecode information in a multiprocessor system Dec 17, 1997 Issued
Array ( [id] => 1466304 [patent_doc_number] => 06393548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Variable 16 or 32 bit PCI interface which supports steering and swapping of data' [patent_app_type] => B1 [patent_app_number] => 08/993046 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 10125 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393548.pdf [firstpage_image] =>[orig_patent_app_number] => 08993046 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993046
Variable 16 or 32 bit PCI interface which supports steering and swapping of data Dec 17, 1997 Issued
Array ( [id] => 4352397 [patent_doc_number] => 06314530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Processor having a trace access instruction to access on-chip trace memory' [patent_app_type] => 1 [patent_app_number] => 8/991970 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 12923 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314530.pdf [firstpage_image] =>[orig_patent_app_number] => 991970 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991970
Processor having a trace access instruction to access on-chip trace memory Dec 16, 1997 Issued
Array ( [id] => 4202742 [patent_doc_number] => 06094729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Debug interface including a compact trace record storage' [patent_app_type] => 1 [patent_app_number] => 8/992361 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 18587 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094729.pdf [firstpage_image] =>[orig_patent_app_number] => 992361 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992361
Debug interface including a compact trace record storage Dec 16, 1997 Issued
Array ( [id] => 4318132 [patent_doc_number] => 06182210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Processor having multiple program counters and trace buffers outside an execution pipeline' [patent_app_type] => 1 [patent_app_number] => 8/992375 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 38 [patent_no_of_words] => 16094 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182210.pdf [firstpage_image] =>[orig_patent_app_number] => 992375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992375
Processor having multiple program counters and trace buffers outside an execution pipeline Dec 15, 1997 Issued
Array ( [id] => 4147829 [patent_doc_number] => 06128724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Computation using codes for controlling configurable computational circuit' [patent_app_type] => 1 [patent_app_number] => 8/988703 [patent_app_country] => US [patent_app_date] => 1997-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7871 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128724.pdf [firstpage_image] =>[orig_patent_app_number] => 988703 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/988703
Computation using codes for controlling configurable computational circuit Dec 10, 1997 Issued
Array ( [id] => 3945230 [patent_doc_number] => 05935241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Multiple global pattern history tables for branch prediction in a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/987951 [patent_app_country] => US [patent_app_date] => 1997-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11203 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935241.pdf [firstpage_image] =>[orig_patent_app_number] => 987951 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/987951
Multiple global pattern history tables for branch prediction in a microprocessor Dec 9, 1997 Issued
Array ( [id] => 4223456 [patent_doc_number] => 06078965 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Transmission line system for printed circuits' [patent_app_type] => 1 [patent_app_number] => 8/986968 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 5051 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078965.pdf [firstpage_image] =>[orig_patent_app_number] => 986968 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/986968
Transmission line system for printed circuits Dec 7, 1997 Issued
Array ( [id] => 3961801 [patent_doc_number] => 05974525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'System for allowing multiple instructions to use the same logical registers by remapping them to separate physical segment registers when the first is being utilized' [patent_app_type] => 1 [patent_app_number] => 8/985615 [patent_app_country] => US [patent_app_date] => 1997-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974525.pdf [firstpage_image] =>[orig_patent_app_number] => 985615 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/985615
System for allowing multiple instructions to use the same logical registers by remapping them to separate physical segment registers when the first is being utilized Dec 4, 1997 Issued
08/982575 HIGH-PERFORMANCE AND HIGHLY INTEGRATED COMPUTER ARCHITECTURE WITH EXTENDIBLE EMBEDDED MEMORY Nov 30, 1997 Abandoned
Array ( [id] => 4260235 [patent_doc_number] => 06092180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method for measuring latencies by randomly selected sampling of the instructions while the instruction are executed' [patent_app_type] => 1 [patent_app_number] => 8/980035 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 15258 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092180.pdf [firstpage_image] =>[orig_patent_app_number] => 980035 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/980035
Method for measuring latencies by randomly selected sampling of the instructions while the instruction are executed Nov 25, 1997 Issued
Array ( [id] => 3973987 [patent_doc_number] => 05978925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'System for improving processing efficiency in a pipeline by delaying a clock signal to a program counter and an instruction memory behind a system clock' [patent_app_type] => 1 [patent_app_number] => 8/979850 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4354 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978925.pdf [firstpage_image] =>[orig_patent_app_number] => 979850 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979850
System for improving processing efficiency in a pipeline by delaying a clock signal to a program counter and an instruction memory behind a system clock Nov 25, 1997 Issued
Array ( [id] => 4257134 [patent_doc_number] => 06081885 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method and apparatus for halting a processor and providing state visibility on a pipeline phase basis' [patent_app_type] => 1 [patent_app_number] => 8/974014 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 69 [patent_no_of_words] => 41436 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081885.pdf [firstpage_image] =>[orig_patent_app_number] => 974014 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974014
Method and apparatus for halting a processor and providing state visibility on a pipeline phase basis Nov 18, 1997 Issued
Array ( [id] => 4424790 [patent_doc_number] => 06230252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Hybrid hypercube/torus architecture' [patent_app_type] => 1 [patent_app_number] => 8/971588 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 11834 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230252.pdf [firstpage_image] =>[orig_patent_app_number] => 971588 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/971588
Hybrid hypercube/torus architecture Nov 16, 1997 Issued
Array ( [id] => 4176849 [patent_doc_number] => 06157996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space' [patent_app_type] => 1 [patent_app_number] => 8/969779 [patent_app_country] => US [patent_app_date] => 1997-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 9995 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157996.pdf [firstpage_image] =>[orig_patent_app_number] => 969779 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/969779
Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space Nov 12, 1997 Issued
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