Search

Mackly Monestime

Examiner (ID: 3491)

Most Active Art Unit
2676
Art Unit(s)
2671, 2676, 2783, 2674, 2183
Total Applications
304
Issued Applications
271
Pending Applications
18
Abandoned Applications
15

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4199314 [patent_doc_number] => 06038658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Methods and apparatus to minimize the number of stall latches in a pipeline' [patent_app_type] => 1 [patent_app_number] => 8/962811 [patent_app_country] => US [patent_app_date] => 1997-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4191 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038658.pdf [firstpage_image] =>[orig_patent_app_number] => 962811 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962811
Methods and apparatus to minimize the number of stall latches in a pipeline Nov 2, 1997 Issued
Array ( [id] => 4225958 [patent_doc_number] => 06029241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Processor architecture scheme having multiple bank address override sources for supplying address values and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/959405 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2697 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029241.pdf [firstpage_image] =>[orig_patent_app_number] => 959405 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959405
Processor architecture scheme having multiple bank address override sources for supplying address values and method therefor Oct 27, 1997 Issued
Array ( [id] => 4255318 [patent_doc_number] => 06119221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Instruction prefetching apparatus and instruction prefetching method for processing in a processor' [patent_app_type] => 1 [patent_app_number] => 8/959303 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8903 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119221.pdf [firstpage_image] =>[orig_patent_app_number] => 959303 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959303
Instruction prefetching apparatus and instruction prefetching method for processing in a processor Oct 27, 1997 Issued
Array ( [id] => 4040915 [patent_doc_number] => 05884089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Method for calculating an L1 norm and parallel computer processor' [patent_app_type] => 1 [patent_app_number] => 8/949975 [patent_app_country] => US [patent_app_date] => 1997-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7593 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/884/05884089.pdf [firstpage_image] =>[orig_patent_app_number] => 949975 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/949975
Method for calculating an L1 norm and parallel computer processor Oct 13, 1997 Issued
Array ( [id] => 4148859 [patent_doc_number] => 06016543 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Microprocessor for controlling the conditional execution of instructions' [patent_app_type] => 1 [patent_app_number] => 8/942295 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 41 [patent_no_of_words] => 30700 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016543.pdf [firstpage_image] =>[orig_patent_app_number] => 942295 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942295
Microprocessor for controlling the conditional execution of instructions Sep 30, 1997 Issued
Array ( [id] => 4317977 [patent_doc_number] => 06185676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method and apparatus for performing early branch prediction in a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/940435 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4847 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185676.pdf [firstpage_image] =>[orig_patent_app_number] => 940435 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940435
Method and apparatus for performing early branch prediction in a microprocessor Sep 29, 1997 Issued
Array ( [id] => 4177388 [patent_doc_number] => 06105121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Data processing and data transmission system' [patent_app_type] => 1 [patent_app_number] => 8/926250 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1492 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105121.pdf [firstpage_image] =>[orig_patent_app_number] => 926250 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/926250
Data processing and data transmission system Sep 4, 1997 Issued
08/923187 IC WITH DUAL FUNCTION CLOCK AND DEVICE ID CIRCUIT Sep 3, 1997 Abandoned
Array ( [id] => 4073052 [patent_doc_number] => 06024477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Process and device for an accelerated execution of a program using a stored-program controller' [patent_app_type] => 1 [patent_app_number] => 8/918764 [patent_app_country] => US [patent_app_date] => 1997-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3425 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/024/06024477.pdf [firstpage_image] =>[orig_patent_app_number] => 918764 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/918764
Process and device for an accelerated execution of a program using a stored-program controller Aug 24, 1997 Issued
Array ( [id] => 3989891 [patent_doc_number] => 05905904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Parallel data processing system and method of controlling such a system' [patent_app_type] => 1 [patent_app_number] => 8/906685 [patent_app_country] => US [patent_app_date] => 1997-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2613 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905904.pdf [firstpage_image] =>[orig_patent_app_number] => 906685 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/906685
Parallel data processing system and method of controlling such a system Aug 4, 1997 Issued
Array ( [id] => 4015047 [patent_doc_number] => 05923890 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Method and apparatus for optimizing the handling of synchronous requests to a coupling facility in a sysplex configuration' [patent_app_type] => 1 [patent_app_number] => 8/903285 [patent_app_country] => US [patent_app_date] => 1997-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3834 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923890.pdf [firstpage_image] =>[orig_patent_app_number] => 903285 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/903285
Method and apparatus for optimizing the handling of synchronous requests to a coupling facility in a sysplex configuration Jul 29, 1997 Issued
Array ( [id] => 4206808 [patent_doc_number] => 06131153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Multiprocessor system having a plurality of gateway units and wherein each gateway unit controls memory access requests and interferences from one hierchical level to another' [patent_app_type] => 1 [patent_app_number] => 8/817934 [patent_app_country] => US [patent_app_date] => 1997-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4710 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/131/06131153.pdf [firstpage_image] =>[orig_patent_app_number] => 817934 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/817934
Multiprocessor system having a plurality of gateway units and wherein each gateway unit controls memory access requests and interferences from one hierchical level to another Jul 10, 1997 Issued
Array ( [id] => 3983665 [patent_doc_number] => 05887134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'System and method for preserving message order while employing both programmed I/O and DMA operations' [patent_app_type] => 1 [patent_app_number] => 8/885151 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 12924 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887134.pdf [firstpage_image] =>[orig_patent_app_number] => 885151 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885151
System and method for preserving message order while employing both programmed I/O and DMA operations Jun 29, 1997 Issued
Array ( [id] => 4121443 [patent_doc_number] => 06023753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Manifold array processor' [patent_app_type] => 1 [patent_app_number] => 8/885310 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 45 [patent_no_of_words] => 8634 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023753.pdf [firstpage_image] =>[orig_patent_app_number] => 885310 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885310
Manifold array processor Jun 29, 1997 Issued
Array ( [id] => 4063683 [patent_doc_number] => 05964862 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Execution unit and method for using architectural and working register files to reduce operand bypasses' [patent_app_type] => 1 [patent_app_number] => 8/884699 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9222 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 375 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/964/05964862.pdf [firstpage_image] =>[orig_patent_app_number] => 884699 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884699
Execution unit and method for using architectural and working register files to reduce operand bypasses Jun 29, 1997 Issued
Array ( [id] => 3915430 [patent_doc_number] => 05944810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Superscalar processor for retiring multiple instructions in working register file by changing the status bits associated with each execution result to identify valid data' [patent_app_type] => 1 [patent_app_number] => 8/883125 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3321 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/944/05944810.pdf [firstpage_image] =>[orig_patent_app_number] => 883125 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883125
Superscalar processor for retiring multiple instructions in working register file by changing the status bits associated with each execution result to identify valid data Jun 26, 1997 Issued
Array ( [id] => 4239253 [patent_doc_number] => 06088786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method and system for coupling a stack based processor to register based functional unit' [patent_app_type] => 1 [patent_app_number] => 8/884255 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6607 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088786.pdf [firstpage_image] =>[orig_patent_app_number] => 884255 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884255
Method and system for coupling a stack based processor to register based functional unit Jun 26, 1997 Issued
Array ( [id] => 4351115 [patent_doc_number] => 06334193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Method and apparatus for implementing user-definable error handling processes' [patent_app_type] => 1 [patent_app_number] => 8/865527 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4094 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/334/06334193.pdf [firstpage_image] =>[orig_patent_app_number] => 865527 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865527
Method and apparatus for implementing user-definable error handling processes May 28, 1997 Issued
Array ( [id] => 1360528 [patent_doc_number] => 06587867 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Internet-based subscriber profile management of a communications system' [patent_app_type] => B1 [patent_app_number] => 08/862134 [patent_app_country] => US [patent_app_date] => 1997-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 10108 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587867.pdf [firstpage_image] =>[orig_patent_app_number] => 08862134 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/862134
Internet-based subscriber profile management of a communications system May 21, 1997 Issued
Array ( [id] => 1406931 [patent_doc_number] => 06560692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Data processing circuit, microcomputer, and electronic equipment' [patent_app_type] => B1 [patent_app_number] => 08/859490 [patent_app_country] => US [patent_app_date] => 1997-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 33 [patent_no_of_words] => 17154 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560692.pdf [firstpage_image] =>[orig_patent_app_number] => 08859490 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/859490
Data processing circuit, microcomputer, and electronic equipment May 19, 1997 Issued
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