
Mackly Monestime
Examiner (ID: 3491)
| Most Active Art Unit | 2676 |
| Art Unit(s) | 2671, 2676, 2783, 2674, 2183 |
| Total Applications | 304 |
| Issued Applications | 271 |
| Pending Applications | 18 |
| Abandoned Applications | 15 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4007612
[patent_doc_number] => 05892893
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Device for the bus-networked operation of an electronic unit with microcontroller, and its use'
[patent_app_type] => 1
[patent_app_number] => 8/825027
[patent_app_country] => US
[patent_app_date] => 1997-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 12523
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 309
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/892/05892893.pdf
[firstpage_image] =>[orig_patent_app_number] => 825027
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/825027 | Device for the bus-networked operation of an electronic unit with microcontroller, and its use | Mar 25, 1997 | Issued |
Array
(
[id] => 4199551
[patent_doc_number] => 06094532
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-25
[patent_title] => 'Multiprocessor distributed memory system and board and methods therefor'
[patent_app_type] => 1
[patent_app_number] => 8/826805
[patent_app_country] => US
[patent_app_date] => 1997-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 16286
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[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/094/06094532.pdf
[firstpage_image] =>[orig_patent_app_number] => 826805
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/826805 | Multiprocessor distributed memory system and board and methods therefor | Mar 24, 1997 | Issued |
Array
(
[id] => 3996332
[patent_doc_number] => 05911082
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-08
[patent_title] => 'Parallel processing building block chip'
[patent_app_type] => 1
[patent_app_number] => 8/810140
[patent_app_country] => US
[patent_app_date] => 1997-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4636
[patent_no_of_claims] => 26
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[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/911/05911082.pdf
[firstpage_image] =>[orig_patent_app_number] => 810140
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/810140 | Parallel processing building block chip | Feb 24, 1997 | Issued |
Array
(
[id] => 3989881
[patent_doc_number] => 05905903
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'PC card for an ISDN interface'
[patent_app_type] => 1
[patent_app_number] => 8/802817
[patent_app_country] => US
[patent_app_date] => 1997-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3317
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/905/05905903.pdf
[firstpage_image] =>[orig_patent_app_number] => 802817
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/802817 | PC card for an ISDN interface | Feb 18, 1997 | Issued |
Array
(
[id] => 3895542
[patent_doc_number] => 05765033
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'System for routing electronic mails'
[patent_app_type] => 1
[patent_app_number] => 8/795680
[patent_app_country] => US
[patent_app_date] => 1997-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2996
[patent_no_of_claims] => 11
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[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/765/05765033.pdf
[firstpage_image] =>[orig_patent_app_number] => 795680
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/795680 | System for routing electronic mails | Feb 5, 1997 | Issued |
Array
(
[id] => 3807491
[patent_doc_number] => 05842034
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Two dimensional crossbar mesh for multi-processor interconnect'
[patent_app_type] => 1
[patent_app_number] => 8/770401
[patent_app_country] => US
[patent_app_date] => 1996-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2909
[patent_no_of_claims] => 16
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/842/05842034.pdf
[firstpage_image] =>[orig_patent_app_number] => 770401
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/770401 | Two dimensional crossbar mesh for multi-processor interconnect | Dec 19, 1996 | Issued |
Array
(
[id] => 4063669
[patent_doc_number] => 05964861
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-12
[patent_title] => 'Method for writing a program to control processors using any instructions selected from original instructions and defining the instructions used as a new instruction set'
[patent_app_type] => 1
[patent_app_number] => 8/767644
[patent_app_country] => US
[patent_app_date] => 1996-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3237
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/964/05964861.pdf
[firstpage_image] =>[orig_patent_app_number] => 767644
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/767644 | Method for writing a program to control processors using any instructions selected from original instructions and defining the instructions used as a new instruction set | Dec 16, 1996 | Issued |
Array
(
[id] => 3755786
[patent_doc_number] => 05787273
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-28
[patent_title] => 'Multiple parallel identical finite state machines which share combinatorial logic'
[patent_app_type] => 1
[patent_app_number] => 8/764212
[patent_app_country] => US
[patent_app_date] => 1996-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3503
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/787/05787273.pdf
[firstpage_image] =>[orig_patent_app_number] => 764212
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/764212 | Multiple parallel identical finite state machines which share combinatorial logic | Dec 12, 1996 | Issued |
| 08/746881 | MODULAR COMPUTATIONAL STRUCTURE THAT SUPPORTS INSTRUCTIONS FOR VIDEO PROCESSING | Nov 17, 1996 | Abandoned |
Array
(
[id] => 4008660
[patent_doc_number] => 05892962
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'FPGA-based processor'
[patent_app_type] => 1
[patent_app_number] => 8/748041
[patent_app_country] => US
[patent_app_date] => 1996-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 5182
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[pdf_file] => patents/05/892/05892962.pdf
[firstpage_image] =>[orig_patent_app_number] => 748041
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/748041 | FPGA-based processor | Nov 11, 1996 | Issued |
Array
(
[id] => 4042663
[patent_doc_number] => 05903768
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-11
[patent_title] => 'Pipelined Microprocessor and load address prediction method therefor'
[patent_app_type] => 1
[patent_app_number] => 8/742911
[patent_app_country] => US
[patent_app_date] => 1996-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 21
[patent_no_of_words] => 10188
[patent_no_of_claims] => 18
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/903/05903768.pdf
[firstpage_image] =>[orig_patent_app_number] => 742911
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/742911 | Pipelined Microprocessor and load address prediction method therefor | Oct 31, 1996 | Issued |
| 08/741542 | METHOD AND APPARATUS FOR PERFORMING INPUT/OUTPUT OPERATIONS BETWEEN REQUESTING DEVICE AND RESPONDING DEVICE | Oct 30, 1996 | Abandoned |
Array
(
[id] => 3984411
[patent_doc_number] => 05887180
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-23
[patent_title] => 'Pattern recognition with N processors'
[patent_app_type] => 1
[patent_app_number] => 8/702496
[patent_app_country] => US
[patent_app_date] => 1996-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3860
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[pdf_file] => patents/05/887/05887180.pdf
[firstpage_image] =>[orig_patent_app_number] => 702496
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/702496 | Pattern recognition with N processors | Oct 27, 1996 | Issued |
Array
(
[id] => 3858066
[patent_doc_number] => 05848294
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'PCI computer system with multiple legacy devices'
[patent_app_type] => 1
[patent_app_number] => 8/730881
[patent_app_country] => US
[patent_app_date] => 1996-10-17
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[pdf_file] => patents/05/848/05848294.pdf
[firstpage_image] =>[orig_patent_app_number] => 730881
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/730881 | PCI computer system with multiple legacy devices | Oct 16, 1996 | Issued |
Array
(
[id] => 4008721
[patent_doc_number] => 05892968
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Multimedia data transferring method'
[patent_app_type] => 1
[patent_app_number] => 8/729839
[patent_app_country] => US
[patent_app_date] => 1996-10-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/892/05892968.pdf
[firstpage_image] =>[orig_patent_app_number] => 729839
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/729839 | Multimedia data transferring method | Oct 14, 1996 | Issued |
Array
(
[id] => 3905389
[patent_doc_number] => 05778244
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-07
[patent_title] => 'Digital signal processing unit using digital signal processor array with recirculation'
[patent_app_type] => 1
[patent_app_number] => 8/726632
[patent_app_country] => US
[patent_app_date] => 1996-10-07
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/778/05778244.pdf
[firstpage_image] =>[orig_patent_app_number] => 726632
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/726632 | Digital signal processing unit using digital signal processor array with recirculation | Oct 6, 1996 | Issued |
Array
(
[id] => 4057830
[patent_doc_number] => 05875346
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-23
[patent_title] => 'System for restoring register data in a pipelined data processing system using latch feedback assemblies'
[patent_app_type] => 1
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[pdf_file] => patents/05/875/05875346.pdf
[firstpage_image] =>[orig_patent_app_number] => 713903
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/713903 | System for restoring register data in a pipelined data processing system using latch feedback assemblies | Sep 12, 1996 | Issued |
Array
(
[id] => 4068594
[patent_doc_number] => 05970229
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Apparatus and method for performing look-ahead scheduling of DMA transfers of data from a host memory to a transmit buffer memory'
[patent_app_type] => 1
[patent_app_number] => 8/707896
[patent_app_country] => US
[patent_app_date] => 1996-09-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/970/05970229.pdf
[firstpage_image] =>[orig_patent_app_number] => 707896
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/707896 | Apparatus and method for performing look-ahead scheduling of DMA transfers of data from a host memory to a transmit buffer memory | Sep 11, 1996 | Issued |
Array
(
[id] => 4057533
[patent_doc_number] => 05996058
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'System and method for handling software interrupts with argument passing'
[patent_app_type] => 1
[patent_app_number] => 8/699295
[patent_app_country] => US
[patent_app_date] => 1996-08-19
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[pdf_file] => patents/05/996/05996058.pdf
[firstpage_image] =>[orig_patent_app_number] => 699295
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/699295 | System and method for handling software interrupts with argument passing | Aug 18, 1996 | Issued |
Array
(
[id] => 3761529
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-01
[patent_title] => 'Extended DLUR/APPN support for non-APPN SNA devices'
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[patent_app_number] => 8/702392
[patent_app_country] => US
[patent_app_date] => 1996-08-14
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[pdf_file] => patents/05/802/05802313.pdf
[firstpage_image] =>[orig_patent_app_number] => 702392
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/702392 | Extended DLUR/APPN support for non-APPN SNA devices | Aug 13, 1996 | Issued |