Magid Y. Dimyan

Array ( [id] => 5317781 [patent_doc_number] => 20090282379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'SYSTEM AND METHOD FOR CIRCUIT SCHEMATIC GENERATION' [patent_app_type] => utility [patent_app_number] => 12/118558 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12608 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282379.pdf [firstpage_image] =>[orig_patent_app_number] => 12118558 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4780903 [patent_doc_number] => 20080288902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'CIRCUIT DESIGN VERIFICATION METHOD AND APPARATUS AND COMPUTER READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/117018 [patent_app_country] => US [patent_app_date] => 2008-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20080288902.pdf [firstpage_image] =>[orig_patent_app_number] => 12117018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5486978 [patent_doc_number] => 20090276743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'SYSTEM AND METHOD FOR COMPUTING PROXY SLACK DURING STATISTIC ANALYSIS OF DIGITAL INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/113288 [patent_app_country] => US [patent_app_date] => 2008-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3589 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20090276743.pdf [firstpage_image] =>[orig_patent_app_number] => 12113288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5587264 [patent_doc_number] => 20090106466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'DESIGN STRUCTURE FOR PIGGYBACKING MULTIPLE DATA TENURES ON A SINGLE DATA BUS GRANT TO ACHIEVE HIGHER BUS UTILIZATION' [patent_app_type] => utility [patent_app_number] => 12/112818 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20090106466.pdf [firstpage_image] =>[orig_patent_app_number] => 12112818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7993381 [patent_doc_number] => 08078999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Structure for implementing speculative clock gating of digital logic circuits' [patent_app_type] => utility [patent_app_number] => 12/112063 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3953 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/078/08078999.pdf [firstpage_image] =>[orig_patent_app_number] => 12112063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7972377 [patent_doc_number] => 07941767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Photomask management method and photomask wash limit generating method' [patent_app_type] => utility [patent_app_number] => 12/112688 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 13161 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941767.pdf [firstpage_image] =>[orig_patent_app_number] => 12112688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4889153 [patent_doc_number] => 20080263485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Verification support method and apparatus, and computer product' [patent_app_type] => utility [patent_app_number] => 12/081417 [patent_app_country] => US [patent_app_date] => 2008-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4558 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263485.pdf [firstpage_image] =>[orig_patent_app_number] => 12081417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5459831 [patent_doc_number] => 20090259983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-15 [patent_title] => 'METHODS FOR DESIGNING A PRODUCT CHIP A PRIORI FOR DESIGN SUBSETTING, FEATURE ANALYSIS, AND YIELD LEARNING' [patent_app_type] => utility [patent_app_number] => 12/103217 [patent_app_country] => US [patent_app_date] => 2008-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2426 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20090259983.pdf [firstpage_image] =>[orig_patent_app_number] => 12103217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4814709 [patent_doc_number] => 20080195340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'Performing temporal checking' [patent_app_type] => utility [patent_app_number] => 12/102525 [patent_app_country] => US [patent_app_date] => 2008-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2507 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20080195340.pdf [firstpage_image] =>[orig_patent_app_number] => 12102525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4462801 [patent_doc_number] => 07895557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Concurrent buffering and layer assignment in integrated circuit layout' [patent_app_type] => utility [patent_app_number] => 12/100477 [patent_app_country] => US [patent_app_date] => 2008-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2707 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/895/07895557.pdf [firstpage_image] =>[orig_patent_app_number] => 12100477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 276156 [patent_doc_number] => 07562331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-14 [patent_title] => 'Netlist synthesis and automatic generation of PC board schematics' [patent_app_type] => utility [patent_app_number] => 12/101068 [patent_app_country] => US [patent_app_date] => 2008-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5623 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/562/07562331.pdf [firstpage_image] =>[orig_patent_app_number] => 12101068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4665591 [patent_doc_number] => 20080256498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'Method and apparatus for logic equivalence verification, and computer product' [patent_app_type] => utility [patent_app_number] => 12/081127 [patent_app_country] => US [patent_app_date] => 2008-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5699 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20080256498.pdf [firstpage_image] =>[orig_patent_app_number] => 12081127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4722919 [patent_doc_number] => 20080244496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'LAYOUT DESIGN DEVICE AND LAYOUT METHOD' [patent_app_type] => utility [patent_app_number] => 12/059307 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2579 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244496.pdf [firstpage_image] =>[orig_patent_app_number] => 12059307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5405766 [patent_doc_number] => 20090241081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'REVERSE DONUT MODEL' [patent_app_type] => utility [patent_app_number] => 12/054317 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8434 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20090241081.pdf [firstpage_image] =>[orig_patent_app_number] => 12054317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5405763 [patent_doc_number] => 20090241078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'METHODS FOR CONSERVING MEMORY IN STATISTICAL STATIC TIMING ANALYSIS' [patent_app_type] => utility [patent_app_number] => 12/053887 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3584 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20090241078.pdf [firstpage_image] =>[orig_patent_app_number] => 12053887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4642097 [patent_doc_number] => 08020133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Semiconductor integrated circuit with multi-cut via and automated layout method for the same' [patent_app_type] => utility [patent_app_number] => 12/076637 [patent_app_country] => US [patent_app_date] => 2008-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4984 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/020/08020133.pdf [firstpage_image] =>[orig_patent_app_number] => 12076637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4441500 [patent_doc_number] => 07971176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Method for testing integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/050207 [patent_app_country] => US [patent_app_date] => 2008-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7304 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971176.pdf [firstpage_image] =>[orig_patent_app_number] => 12050207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7593622 [patent_doc_number] => 07627845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-01 [patent_title] => 'Macrocell, integrated circuit device, and electronic instrument' [patent_app_type] => utility [patent_app_number] => 12/071466 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 12849 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/627/07627845.pdf [firstpage_image] =>[orig_patent_app_number] => 12071466 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5393517 [patent_doc_number] => 20090210830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'SYSTEM AND METHOD FOR ESTIMATING TEST ESCAPES IN INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/032557 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5663 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210830.pdf [firstpage_image] =>[orig_patent_app_number] => 12032557 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4874946 [patent_doc_number] => 20080201680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'DESIGNING APPARATUS, DESIGNING METHOD, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/032347 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6798 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20080201680.pdf [firstpage_image] =>[orig_patent_app_number] => 12032347 [rel_patent_id] =>[rel_patent_doc_number] =>)