Magid Y. Dimyan

Array ( [id] => 4837137 [patent_doc_number] => 20080134115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'METASTABILITY EFFECTS SIMULATION FOR A CIRCUIT DESCRIPTION' [patent_app_type] => utility [patent_app_number] => 12/029440 [patent_app_country] => US [patent_app_date] => 2008-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 20746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20080134115.pdf [firstpage_image] =>[orig_patent_app_number] => 12029440 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1078951 [patent_doc_number] => 07617472 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-11-10 [patent_title] => 'Regional signal-distribution network for an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/025637 [patent_app_country] => US [patent_app_date] => 2008-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7126 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/617/07617472.pdf [firstpage_image] =>[orig_patent_app_number] => 12025637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4449112 [patent_doc_number] => 07865864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Electrically driven optical proximity correction' [patent_app_type] => utility [patent_app_number] => 12/024188 [patent_app_country] => US [patent_app_date] => 2008-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5420 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865864.pdf [firstpage_image] =>[orig_patent_app_number] => 12024188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4441442 [patent_doc_number] => 07971161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Apparatus and method for implementing speculative clock gating of digital logic circuits' [patent_app_type] => utility [patent_app_number] => 12/019718 [patent_app_country] => US [patent_app_date] => 2008-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3610 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971161.pdf [firstpage_image] =>[orig_patent_app_number] => 12019718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 76748 [patent_doc_number] => 07757192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => 'Integrated circuit designing device, integrated circuit designing method, and integrated circuit designing program' [patent_app_type] => utility [patent_app_number] => 12/019208 [patent_app_country] => US [patent_app_date] => 2008-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8738 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/757/07757192.pdf [firstpage_image] =>[orig_patent_app_number] => 12019208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4441437 [patent_doc_number] => 07971160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Creating method of photomask pattern data, photomask created by using the photomask pattern data, and manufacturing method of semiconductor apparatus using the photomask' [patent_app_type] => utility [patent_app_number] => 12/017658 [patent_app_country] => US [patent_app_date] => 2008-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13488 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971160.pdf [firstpage_image] =>[orig_patent_app_number] => 12017658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5356530 [patent_doc_number] => 20090187874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'CIRCUIT AND CIRCUIT DESIGN METHOD' [patent_app_type] => utility [patent_app_number] => 12/015627 [patent_app_country] => US [patent_app_date] => 2008-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20090187874.pdf [firstpage_image] =>[orig_patent_app_number] => 12015627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4550701 [patent_doc_number] => 07926001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Uniformity for semiconductor patterning operations' [patent_app_type] => utility [patent_app_number] => 12/014958 [patent_app_country] => US [patent_app_date] => 2008-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8055 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/926/07926001.pdf [firstpage_image] =>[orig_patent_app_number] => 12014958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4558667 [patent_doc_number] => 07890917 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-15 [patent_title] => 'Method and apparatus for providing secure intellectual property cores for a programmable logic device' [patent_app_type] => utility [patent_app_number] => 12/008848 [patent_app_country] => US [patent_app_date] => 2008-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/890/07890917.pdf [firstpage_image] =>[orig_patent_app_number] => 12008848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5344477 [patent_doc_number] => 20090183127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'Method and Apparatus for Evaluating Integrated Circuit Design Performance Using Enhanced Basic Block Vectors that Include Data Dependent Information' [patent_app_type] => utility [patent_app_number] => 11/972747 [patent_app_country] => US [patent_app_date] => 2008-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10054 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20090183127.pdf [firstpage_image] =>[orig_patent_app_number] => 11972747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4591306 [patent_doc_number] => 07827516 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-02 [patent_title] => 'Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patterns' [patent_app_type] => utility [patent_app_number] => 11/969214 [patent_app_country] => US [patent_app_date] => 2008-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 5611 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/827/07827516.pdf [firstpage_image] =>[orig_patent_app_number] => 11969214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 127067 [patent_doc_number] => 07712071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Printing a mask with maximum possible process window through adjustment of the source distribution' [patent_app_type] => utility [patent_app_number] => 11/957587 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 13761 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/712/07712071.pdf [firstpage_image] =>[orig_patent_app_number] => 11957587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4747494 [patent_doc_number] => 20080092096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'METHOD AND SYSTEM FOR OPTIMIZED AUTOMATED CASE-SPLITTING VIA CONSTRAINTS IN A SYMBOLIC SIMULATION FRAMEWORK' [patent_app_type] => utility [patent_app_number] => 11/954626 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9570 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20080092096.pdf [firstpage_image] =>[orig_patent_app_number] => 11954626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4499703 [patent_doc_number] => 07886263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-08 [patent_title] => 'Testing to prescribe state capture by, and state retrieval from scan registers' [patent_app_type] => utility [patent_app_number] => 11/953227 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 9164 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/886/07886263.pdf [firstpage_image] =>[orig_patent_app_number] => 11953227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4582566 [patent_doc_number] => 07840927 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-23 [patent_title] => 'Mutable cells for use in integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/953048 [patent_app_country] => US [patent_app_date] => 2007-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 14002 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840927.pdf [firstpage_image] =>[orig_patent_app_number] => 11953048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4590550 [patent_doc_number] => 07831950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Method and system for designing printed circuit board for electronic circuit' [patent_app_type] => utility [patent_app_number] => 11/951514 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6303 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/831/07831950.pdf [firstpage_image] =>[orig_patent_app_number] => 11951514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 107100 [patent_doc_number] => 07730443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'System and method for checking a length of a wire path between a capacitor and a via of a PCB design' [patent_app_type] => utility [patent_app_number] => 11/951284 [patent_app_country] => US [patent_app_date] => 2007-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1858 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/730/07730443.pdf [firstpage_image] =>[orig_patent_app_number] => 11951284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4574185 [patent_doc_number] => 07962885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testing' [patent_app_type] => utility [patent_app_number] => 11/950177 [patent_app_country] => US [patent_app_date] => 2007-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 25663 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/962/07962885.pdf [firstpage_image] =>[orig_patent_app_number] => 11950177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 127033 [patent_doc_number] => 07712055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Designing integrated circuits for yield' [patent_app_type] => utility [patent_app_number] => 11/947737 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4500 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/712/07712055.pdf [firstpage_image] =>[orig_patent_app_number] => 11947737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9101 [patent_doc_number] => 07818692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Automated optimization of device structure during circuit design stage' [patent_app_type] => utility [patent_app_number] => 11/946937 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5007 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/818/07818692.pdf [firstpage_image] =>[orig_patent_app_number] => 11946937 [rel_patent_id] =>[rel_patent_doc_number] =>)