Search

Magid Y. Dimyan

Examiner (ID: 7023)

Most Active Art Unit
2825
Art Unit(s)
2851, 2825
Total Applications
684
Issued Applications
621
Pending Applications
9
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9101 [patent_doc_number] => 07818692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Automated optimization of device structure during circuit design stage' [patent_app_type] => utility [patent_app_number] => 11/946937 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5007 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/818/07818692.pdf [firstpage_image] =>[orig_patent_app_number] => 11946937 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/946937
Automated optimization of device structure during circuit design stage Nov 28, 2007 Issued
Array ( [id] => 4684153 [patent_doc_number] => 20080250379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'LOGIC CIRCUIT SYNTHESIS DEVICE' [patent_app_type] => utility [patent_app_number] => 11/947417 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 68 [patent_no_of_words] => 33743 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250379.pdf [firstpage_image] =>[orig_patent_app_number] => 11947417 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/947417
LOGIC CIRCUIT SYNTHESIS DEVICE Nov 28, 2007 Abandoned
Array ( [id] => 5565983 [patent_doc_number] => 20090138836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'AUTOMATIC VERIFICATION OF ADEQUATE CONDUCTIVE RETURN-CURRENT PATHS' [patent_app_type] => utility [patent_app_number] => 11/945754 [patent_app_country] => US [patent_app_date] => 2007-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20090138836.pdf [firstpage_image] =>[orig_patent_app_number] => 11945754 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/945754
Automatic verification of adequate conductive return-current paths Nov 26, 2007 Issued
Array ( [id] => 4577941 [patent_doc_number] => 07823092 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-26 [patent_title] => 'Method and apparatus for implementing a parameterizable filter block with an electronic design automation tool' [patent_app_type] => utility [patent_app_number] => 11/986607 [patent_app_country] => US [patent_app_date] => 2007-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 12444 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/823/07823092.pdf [firstpage_image] =>[orig_patent_app_number] => 11986607 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/986607
Method and apparatus for implementing a parameterizable filter block with an electronic design automation tool Nov 22, 2007 Issued
Array ( [id] => 4449103 [patent_doc_number] => 07865855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Method and system for generating a layout for an integrated electronic circuit' [patent_app_type] => utility [patent_app_number] => 11/942744 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3881 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865855.pdf [firstpage_image] =>[orig_patent_app_number] => 11942744 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/942744
Method and system for generating a layout for an integrated electronic circuit Nov 19, 2007 Issued
Array ( [id] => 9248617 [patent_doc_number] => 08612919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'Model-based design verification' [patent_app_type] => utility [patent_app_number] => 11/986564 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 15037 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11986564 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/986564
Model-based design verification Nov 19, 2007 Issued
Array ( [id] => 137352 [patent_doc_number] => 07698671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Method for designing semiconductor integrated circuits having air gaps.' [patent_app_type] => utility [patent_app_number] => 11/942384 [patent_app_country] => US [patent_app_date] => 2007-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 41 [patent_no_of_words] => 12112 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698671.pdf [firstpage_image] =>[orig_patent_app_number] => 11942384 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/942384
Method for designing semiconductor integrated circuits having air gaps. Nov 18, 2007 Issued
Array ( [id] => 4747492 [patent_doc_number] => 20080092094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 11/941104 [patent_app_country] => US [patent_app_date] => 2007-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6341 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20080092094.pdf [firstpage_image] =>[orig_patent_app_number] => 11941104 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/941104
Design structure with a deep sub-collector, a reach-through structure and trench isolation Nov 15, 2007 Issued
Array ( [id] => 5411965 [patent_doc_number] => 20090125864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'SYSTEM AND METHOD FOR MAKING PHOTOMASKS' [patent_app_type] => utility [patent_app_number] => 11/940194 [patent_app_country] => US [patent_app_date] => 2007-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5971 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20090125864.pdf [firstpage_image] =>[orig_patent_app_number] => 11940194 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/940194
System and method for making photomasks Nov 13, 2007 Issued
Array ( [id] => 4528394 [patent_doc_number] => 07934179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Systems and methods for logic verification' [patent_app_type] => utility [patent_app_number] => 11/937577 [patent_app_country] => US [patent_app_date] => 2007-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3863 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/934/07934179.pdf [firstpage_image] =>[orig_patent_app_number] => 11937577 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/937577
Systems and methods for logic verification Nov 8, 2007 Issued
Array ( [id] => 66675 [patent_doc_number] => 07765500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Automated generation of theoretical performance analysis based upon workload and design configuration' [patent_app_type] => utility [patent_app_number] => 11/983657 [patent_app_country] => US [patent_app_date] => 2007-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6946 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/765/07765500.pdf [firstpage_image] =>[orig_patent_app_number] => 11983657 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/983657
Automated generation of theoretical performance analysis based upon workload and design configuration Nov 7, 2007 Issued
Array ( [id] => 47991 [patent_doc_number] => 07784019 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-24 [patent_title] => 'Yield based retargeting for semiconductor design flow' [patent_app_type] => utility [patent_app_number] => 11/934047 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 9526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/784/07784019.pdf [firstpage_image] =>[orig_patent_app_number] => 11934047 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/934047
Yield based retargeting for semiconductor design flow Oct 31, 2007 Issued
Array ( [id] => 28586 [patent_doc_number] => 07797658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Multithreaded static timing analysis' [patent_app_type] => utility [patent_app_number] => 11/876688 [patent_app_country] => US [patent_app_date] => 2007-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6405 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797658.pdf [firstpage_image] =>[orig_patent_app_number] => 11876688 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/876688
Multithreaded static timing analysis Oct 21, 2007 Issued
Array ( [id] => 19185 [patent_doc_number] => 07810059 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-05 [patent_title] => 'Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams' [patent_app_type] => utility [patent_app_number] => 11/974387 [patent_app_country] => US [patent_app_date] => 2007-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/810/07810059.pdf [firstpage_image] =>[orig_patent_app_number] => 11974387 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/974387
Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams Oct 10, 2007 Issued
Array ( [id] => 4917733 [patent_doc_number] => 20080098334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features' [patent_app_type] => utility [patent_app_number] => 11/906736 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20080098334.pdf [firstpage_image] =>[orig_patent_app_number] => 11906736 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/906736
Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features Oct 1, 2007 Issued
Array ( [id] => 5430422 [patent_doc_number] => 20090089732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'METHOD AND APPARATUS FOR PERFORMING DUMMY-FILL BY USING A SET OF DUMMY-FILL CELLS' [patent_app_type] => utility [patent_app_number] => 11/863577 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3971 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20090089732.pdf [firstpage_image] =>[orig_patent_app_number] => 11863577 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/863577
Method and apparatus for performing dummy-fill by using a set of dummy-fill cells Sep 27, 2007 Issued
Array ( [id] => 5430414 [patent_doc_number] => 20090089724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'Detection Method for Identifying Unintentionally Forward-Biased Diode Devices in an Integrated Circuit Device Design' [patent_app_type] => utility [patent_app_number] => 11/862887 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6459 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20090089724.pdf [firstpage_image] =>[orig_patent_app_number] => 11862887 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/862887
Detection method for identifying unintentionally forward-biased diode devices in an integrated circuit device design Sep 26, 2007 Issued
Array ( [id] => 172008 [patent_doc_number] => 07669176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'System and method for semiconductor device fabrication using modeling' [patent_app_type] => utility [patent_app_number] => 11/855887 [patent_app_country] => US [patent_app_date] => 2007-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 4975 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669176.pdf [firstpage_image] =>[orig_patent_app_number] => 11855887 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/855887
System and method for semiconductor device fabrication using modeling Sep 13, 2007 Issued
Array ( [id] => 27587 [patent_doc_number] => 07802216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Area and power saving standard cell methodology' [patent_app_type] => utility [patent_app_number] => 11/855077 [patent_app_country] => US [patent_app_date] => 2007-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3474 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802216.pdf [firstpage_image] =>[orig_patent_app_number] => 11855077 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/855077
Area and power saving standard cell methodology Sep 12, 2007 Issued
Array ( [id] => 5449782 [patent_doc_number] => 20090065818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'STRUCTURE FOR IMAGERS HAVING ELECTRICALLY ACTIVE OPTICAL ELEMENTS' [patent_app_type] => utility [patent_app_number] => 11/850807 [patent_app_country] => US [patent_app_date] => 2007-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6792 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20090065818.pdf [firstpage_image] =>[orig_patent_app_number] => 11850807 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/850807
Structure for imagers having electrically active optical elements Sep 5, 2007 Issued
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