Magid Y. Dimyan

Array ( [id] => 7599885 [patent_doc_number] => 07386828 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-06-10 [patent_title] => 'SAT-based technology mapping framework' [patent_app_type] => utility [patent_app_number] => 11/361808 [patent_app_country] => US [patent_app_date] => 2006-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/386/07386828.pdf [firstpage_image] =>[orig_patent_app_number] => 11361808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 806358 [patent_doc_number] => 07424695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-09 [patent_title] => 'Method of manufacturing a semiconductor integrated circuit, a program for a computer automated design system, and a semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/354958 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 36 [patent_no_of_words] => 9312 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/424/07424695.pdf [firstpage_image] =>[orig_patent_app_number] => 11354958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5684062 [patent_doc_number] => 20060200332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'CAD system for a printed circuit board' [patent_app_type] => utility [patent_app_number] => 11/350788 [patent_app_country] => US [patent_app_date] => 2006-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4246 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20060200332.pdf [firstpage_image] =>[orig_patent_app_number] => 11350788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 355770 [patent_doc_number] => 07493576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'CDM ESD event protection in application circuits' [patent_app_type] => utility [patent_app_number] => 11/349356 [patent_app_country] => US [patent_app_date] => 2006-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7226 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/493/07493576.pdf [firstpage_image] =>[orig_patent_app_number] => 11349356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 596079 [patent_doc_number] => 07458044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'CDM ESD event simulation and remediation thereof in application circuits' [patent_app_type] => utility [patent_app_number] => 11/349358 [patent_app_country] => US [patent_app_date] => 2006-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6137 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/458/07458044.pdf [firstpage_image] =>[orig_patent_app_number] => 11349358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5621313 [patent_doc_number] => 20060190848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Low power consumption designing method of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/326577 [patent_app_country] => US [patent_app_date] => 2006-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3548 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190848.pdf [firstpage_image] =>[orig_patent_app_number] => 11326577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4990812 [patent_doc_number] => 20070157153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Yield-limiting design-rules-compliant pattern library generation and layout inspection' [patent_app_type] => utility [patent_app_number] => 11/323468 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3378 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20070157153.pdf [firstpage_image] =>[orig_patent_app_number] => 11323468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 375072 [patent_doc_number] => 07475380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Generating mask patterns for alternating phase-shift mask lithography' [patent_app_type] => utility [patent_app_number] => 11/318893 [patent_app_country] => US [patent_app_date] => 2005-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 30 [patent_no_of_words] => 6910 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475380.pdf [firstpage_image] =>[orig_patent_app_number] => 11318893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 375066 [patent_doc_number] => 07475374 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-06 [patent_title] => 'Clock grid driven by virtual leaf drivers' [patent_app_type] => utility [patent_app_number] => 11/314698 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7679 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475374.pdf [firstpage_image] =>[orig_patent_app_number] => 11314698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 241474 [patent_doc_number] => 07594200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Method for finding multi-cycle clock gating' [patent_app_type] => utility [patent_app_number] => 11/311756 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4178 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/594/07594200.pdf [firstpage_image] =>[orig_patent_app_number] => 11311756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 816696 [patent_doc_number] => 07415686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Memory timing model with back-annotating' [patent_app_type] => utility [patent_app_number] => 11/311388 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7223 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/415/07415686.pdf [firstpage_image] =>[orig_patent_app_number] => 11311388 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5868343 [patent_doc_number] => 20060162960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'SYSTEM FOR DETERMINING PRINTED CIRCUIT BOARD PASSIVE CHANNEL LOSSES' [patent_app_type] => utility [patent_app_number] => 11/306088 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4154 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20060162960.pdf [firstpage_image] =>[orig_patent_app_number] => 11306088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 864576 [patent_doc_number] => 07373630 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-13 [patent_title] => 'Methods for improved structured ASIC design' [patent_app_type] => utility [patent_app_number] => 11/301604 [patent_app_country] => US [patent_app_date] => 2005-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 3482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/373/07373630.pdf [firstpage_image] =>[orig_patent_app_number] => 11301604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 591091 [patent_doc_number] => 07464354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Method and apparatus for performing temporal checking' [patent_app_type] => utility [patent_app_number] => 11/297308 [patent_app_country] => US [patent_app_date] => 2005-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2464 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/464/07464354.pdf [firstpage_image] =>[orig_patent_app_number] => 11297308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 336986 [patent_doc_number] => 07509615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Circuit layout structure and method' [patent_app_type] => utility [patent_app_number] => 11/281477 [patent_app_country] => US [patent_app_date] => 2005-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1501 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509615.pdf [firstpage_image] =>[orig_patent_app_number] => 11281477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 421633 [patent_doc_number] => 07278118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-02 [patent_title] => 'Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features' [patent_app_type] => utility [patent_app_number] => 11/267569 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4036 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/278/07278118.pdf [firstpage_image] =>[orig_patent_app_number] => 11267569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 587394 [patent_doc_number] => 07467359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Decoder using a memory for storing state metrics implementing a decoder trellis' [patent_app_type] => utility [patent_app_number] => 11/266687 [patent_app_country] => US [patent_app_date] => 2005-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 9039 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/467/07467359.pdf [firstpage_image] =>[orig_patent_app_number] => 11266687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 313465 [patent_doc_number] => 07530037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Methods of generating planar double gate transistor shapes and data processing system readable media to perform the methods' [patent_app_type] => utility [patent_app_number] => 11/258777 [patent_app_country] => US [patent_app_date] => 2005-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 10126 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/530/07530037.pdf [firstpage_image] =>[orig_patent_app_number] => 11258777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 340604 [patent_doc_number] => 07506283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-17 [patent_title] => 'System and method for accelerating circuit measurements' [patent_app_type] => utility [patent_app_number] => 11/246527 [patent_app_country] => US [patent_app_date] => 2005-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8796 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/506/07506283.pdf [firstpage_image] =>[orig_patent_app_number] => 11246527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 836512 [patent_doc_number] => 07398500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-08 [patent_title] => 'Netlist synthesis and automatic generation of PC board schematics' [patent_app_type] => utility [patent_app_number] => 11/242151 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5599 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/398/07398500.pdf [firstpage_image] =>[orig_patent_app_number] => 11242151 [rel_patent_id] =>[rel_patent_doc_number] =>)