Search

Magid Y. Dimyan

Examiner (ID: 7023)

Most Active Art Unit
2825
Art Unit(s)
2851, 2825
Total Applications
684
Issued Applications
621
Pending Applications
9
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 877944 [patent_doc_number] => 07363604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'Accurate noise modeling in digital designs' [patent_app_type] => utility [patent_app_number] => 11/240924 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3056 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/363/07363604.pdf [firstpage_image] =>[orig_patent_app_number] => 11240924 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/240924
Accurate noise modeling in digital designs Sep 29, 2005 Issued
Array ( [id] => 5701517 [patent_doc_number] => 20060218202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Structure analytic program' [patent_app_type] => utility [patent_app_number] => 11/237698 [patent_app_country] => US [patent_app_date] => 2005-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 9758 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20060218202.pdf [firstpage_image] =>[orig_patent_app_number] => 11237698 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/237698
Structure analytic program Sep 28, 2005 Issued
Array ( [id] => 895068 [patent_doc_number] => 07350175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-25 [patent_title] => 'Circuit board design system, design data analysis method and recording medium with analysis program recorded thereon' [patent_app_type] => utility [patent_app_number] => 11/238166 [patent_app_country] => US [patent_app_date] => 2005-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 50 [patent_no_of_words] => 22201 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/350/07350175.pdf [firstpage_image] =>[orig_patent_app_number] => 11238166 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/238166
Circuit board design system, design data analysis method and recording medium with analysis program recorded thereon Sep 27, 2005 Issued
Array ( [id] => 843853 [patent_doc_number] => 07392500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-06-24 [patent_title] => 'Structures and methods for reducing power consumption in programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/235997 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4473 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/392/07392500.pdf [firstpage_image] =>[orig_patent_app_number] => 11235997 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/235997
Structures and methods for reducing power consumption in programmable logic devices Sep 26, 2005 Issued
Array ( [id] => 596054 [patent_doc_number] => 07458040 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-11-25 [patent_title] => 'Resettable memory apparatuses and design' [patent_app_type] => utility [patent_app_number] => 11/218400 [patent_app_country] => US [patent_app_date] => 2005-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11458 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/458/07458040.pdf [firstpage_image] =>[orig_patent_app_number] => 11218400 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/218400
Resettable memory apparatuses and design Aug 31, 2005 Issued
Array ( [id] => 5803734 [patent_doc_number] => 20060036974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'IP-based LSI design system and design method' [patent_app_type] => utility [patent_app_number] => 11/211512 [patent_app_country] => US [patent_app_date] => 2005-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5489 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20060036974.pdf [firstpage_image] =>[orig_patent_app_number] => 11211512 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/211512
IP-based LSI design system and design method Aug 25, 2005 Abandoned
Array ( [id] => 7591315 [patent_doc_number] => 07653892 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-01-26 [patent_title] => 'System and method for implementing image-based design rules' [patent_app_type] => utility [patent_app_number] => 11/207266 [patent_app_country] => US [patent_app_date] => 2005-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 13000 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/653/07653892.pdf [firstpage_image] =>[orig_patent_app_number] => 11207266 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207266
System and method for implementing image-based design rules Aug 17, 2005 Issued
Array ( [id] => 813532 [patent_doc_number] => 07418693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-26 [patent_title] => 'System and method for analysis and transformation of layouts using situations' [patent_app_type] => utility [patent_app_number] => 11/207267 [patent_app_country] => US [patent_app_date] => 2005-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7643 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/418/07418693.pdf [firstpage_image] =>[orig_patent_app_number] => 11207267 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207267
System and method for analysis and transformation of layouts using situations Aug 17, 2005 Issued
Array ( [id] => 820203 [patent_doc_number] => 07412675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Hierarchical feature extraction for electrical interaction' [patent_app_type] => utility [patent_app_number] => 11/202935 [patent_app_country] => US [patent_app_date] => 2005-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 5511 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/412/07412675.pdf [firstpage_image] =>[orig_patent_app_number] => 11202935 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/202935
Hierarchical feature extraction for electrical interaction Aug 11, 2005 Issued
Array ( [id] => 925158 [patent_doc_number] => 07320117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-15 [patent_title] => 'Design method for semiconductor integrated circuit device using path isolation' [patent_app_type] => utility [patent_app_number] => 11/167610 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 9900 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/320/07320117.pdf [firstpage_image] =>[orig_patent_app_number] => 11167610 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/167610
Design method for semiconductor integrated circuit device using path isolation Jun 27, 2005 Issued
Array ( [id] => 379198 [patent_doc_number] => 07313776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Method and apparatus for routing an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/169362 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 4512 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313776.pdf [firstpage_image] =>[orig_patent_app_number] => 11169362 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/169362
Method and apparatus for routing an integrated circuit Jun 27, 2005 Issued
Array ( [id] => 5604134 [patent_doc_number] => 20060294481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Method and system for optimized automated case-splitting via constraints in a symbolic simulation framework' [patent_app_type] => utility [patent_app_number] => 11/165455 [patent_app_country] => US [patent_app_date] => 2005-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20060294481.pdf [firstpage_image] =>[orig_patent_app_number] => 11165455 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/165455
Method and system for optimized automated case-splitting via constraints in a symbolic simulation framework Jun 22, 2005 Issued
Array ( [id] => 379196 [patent_doc_number] => 07313774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Method and apparatus for associating an error in a layout with a cell' [patent_app_type] => utility [patent_app_number] => 11/159285 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3659 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313774.pdf [firstpage_image] =>[orig_patent_app_number] => 11159285 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/159285
Method and apparatus for associating an error in a layout with a cell Jun 20, 2005 Issued
Array ( [id] => 400774 [patent_doc_number] => 07296248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Method and apparatus for compiling a parameterized cell' [patent_app_type] => utility [patent_app_number] => 11/157025 [patent_app_country] => US [patent_app_date] => 2005-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3429 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/296/07296248.pdf [firstpage_image] =>[orig_patent_app_number] => 11157025 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/157025
Method and apparatus for compiling a parameterized cell Jun 19, 2005 Issued
Array ( [id] => 5688376 [patent_doc_number] => 20060286691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Capacitance modeling' [patent_app_type] => utility [patent_app_number] => 11/153047 [patent_app_country] => US [patent_app_date] => 2005-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5552 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20060286691.pdf [firstpage_image] =>[orig_patent_app_number] => 11153047 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/153047
Capacitance modeling Jun 14, 2005 Issued
Array ( [id] => 451430 [patent_doc_number] => 07254795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Timing convergence, efficient algorithm to automate swapping of standard devices with low threshold-voltage devices' [patent_app_type] => utility [patent_app_number] => 11/152929 [patent_app_country] => US [patent_app_date] => 2005-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3655 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/254/07254795.pdf [firstpage_image] =>[orig_patent_app_number] => 11152929 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/152929
Timing convergence, efficient algorithm to automate swapping of standard devices with low threshold-voltage devices Jun 14, 2005 Issued
Array ( [id] => 885955 [patent_doc_number] => 07356789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Metastability effects simulation for a circuit description' [patent_app_type] => utility [patent_app_number] => 11/140678 [patent_app_country] => US [patent_app_date] => 2005-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 31 [patent_no_of_words] => 20762 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/356/07356789.pdf [firstpage_image] =>[orig_patent_app_number] => 11140678 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/140678
Metastability effects simulation for a circuit description May 26, 2005 Issued
Array ( [id] => 5774482 [patent_doc_number] => 20050268264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Apparatus and method for calculating crosstalk' [patent_app_type] => utility [patent_app_number] => 11/134387 [patent_app_country] => US [patent_app_date] => 2005-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7069 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20050268264.pdf [firstpage_image] =>[orig_patent_app_number] => 11134387 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/134387
Apparatus and method for calculating crosstalk May 22, 2005 Abandoned
Array ( [id] => 388864 [patent_doc_number] => 07305644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Negative slack recoverability factor—a net weight to enhance timing closure behavior' [patent_app_type] => utility [patent_app_number] => 11/129785 [patent_app_country] => US [patent_app_date] => 2005-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2981 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/305/07305644.pdf [firstpage_image] =>[orig_patent_app_number] => 11129785 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/129785
Negative slack recoverability factor—a net weight to enhance timing closure behavior May 15, 2005 Issued
Array ( [id] => 388850 [patent_doc_number] => 07305638 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-04 [patent_title] => 'Method and system for ROM coding to improve yield' [patent_app_type] => utility [patent_app_number] => 11/128863 [patent_app_country] => US [patent_app_date] => 2005-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5625 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/305/07305638.pdf [firstpage_image] =>[orig_patent_app_number] => 11128863 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/128863
Method and system for ROM coding to improve yield May 12, 2005 Issued
Menu