Search

Magid Y. Dimyan

Examiner (ID: 7023)

Most Active Art Unit
2825
Art Unit(s)
2851, 2825
Total Applications
684
Issued Applications
621
Pending Applications
9
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 388868 [patent_doc_number] => 07305646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Relocatable mixed-signal functions' [patent_app_type] => utility [patent_app_number] => 11/125307 [patent_app_country] => US [patent_app_date] => 2005-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/305/07305646.pdf [firstpage_image] =>[orig_patent_app_number] => 11125307 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/125307
Relocatable mixed-signal functions May 8, 2005 Issued
Array ( [id] => 908896 [patent_doc_number] => 07337426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Pattern correcting method, mask making method, method of manufacturing semiconductor device, pattern correction system, and computer-readable recording medium having pattern correction program recorded therein' [patent_app_type] => utility [patent_app_number] => 11/115187 [patent_app_country] => US [patent_app_date] => 2005-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 14756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/337/07337426.pdf [firstpage_image] =>[orig_patent_app_number] => 11115187 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/115187
Pattern correcting method, mask making method, method of manufacturing semiconductor device, pattern correction system, and computer-readable recording medium having pattern correction program recorded therein Apr 26, 2005 Issued
Array ( [id] => 905230 [patent_doc_number] => 07340710 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-04 [patent_title] => 'Integrated circuit binning and layout design system' [patent_app_type] => utility [patent_app_number] => 11/108507 [patent_app_country] => US [patent_app_date] => 2005-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/340/07340710.pdf [firstpage_image] =>[orig_patent_app_number] => 11108507 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/108507
Integrated circuit binning and layout design system Apr 17, 2005 Issued
Array ( [id] => 832759 [patent_doc_number] => 07401308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-15 [patent_title] => 'Timing analysis apparatus, timing analysis method, and computer product' [patent_app_type] => utility [patent_app_number] => 11/106697 [patent_app_country] => US [patent_app_date] => 2005-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6249 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/401/07401308.pdf [firstpage_image] =>[orig_patent_app_number] => 11106697 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/106697
Timing analysis apparatus, timing analysis method, and computer product Apr 14, 2005 Issued
Array ( [id] => 626574 [patent_doc_number] => 07139991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Automatic method and system for instantiating built-in-test (BIST) modules in ASIC memory designs' [patent_app_type] => utility [patent_app_number] => 11/107585 [patent_app_country] => US [patent_app_date] => 2005-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2825 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139991.pdf [firstpage_image] =>[orig_patent_app_number] => 11107585 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/107585
Automatic method and system for instantiating built-in-test (BIST) modules in ASIC memory designs Apr 13, 2005 Issued
Array ( [id] => 407401 [patent_doc_number] => 07290226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristic' [patent_app_type] => utility [patent_app_number] => 10/907496 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4123 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/290/07290226.pdf [firstpage_image] =>[orig_patent_app_number] => 10907496 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/907496
Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristic Apr 3, 2005 Issued
Array ( [id] => 5755857 [patent_doc_number] => 20060225006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'METHOD AND APPARATUS OF OPTIMIZING THE IO COLLAR OF A PERIPHERAL IMAGE' [patent_app_type] => utility [patent_app_number] => 10/907499 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20060225006.pdf [firstpage_image] =>[orig_patent_app_number] => 10907499 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/907499
Method and apparatus of optimizing the IO collar of a peripheral image Apr 3, 2005 Issued
Array ( [id] => 5853095 [patent_doc_number] => 20060236286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Cost-optimization method' [patent_app_type] => utility [patent_app_number] => 11/089078 [patent_app_country] => US [patent_app_date] => 2005-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2651 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20060236286.pdf [firstpage_image] =>[orig_patent_app_number] => 11089078 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/089078
Cost-optimization method Mar 22, 2005 Issued
Array ( [id] => 407405 [patent_doc_number] => 07290230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'System and method for verifying a digital design using dynamic abstraction' [patent_app_type] => utility [patent_app_number] => 11/082592 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6793 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/290/07290230.pdf [firstpage_image] =>[orig_patent_app_number] => 11082592 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/082592
System and method for verifying a digital design using dynamic abstraction Mar 16, 2005 Issued
Array ( [id] => 797027 [patent_doc_number] => 07430729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-30 [patent_title] => 'Design rule report utility' [patent_app_type] => utility [patent_app_number] => 11/081447 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5410 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/430/07430729.pdf [firstpage_image] =>[orig_patent_app_number] => 11081447 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/081447
Design rule report utility Mar 15, 2005 Issued
Array ( [id] => 5697623 [patent_doc_number] => 20060214307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Method for designing chip package by re-using existing mask designs' [patent_app_type] => utility [patent_app_number] => 11/078781 [patent_app_country] => US [patent_app_date] => 2005-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2758 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20060214307.pdf [firstpage_image] =>[orig_patent_app_number] => 11078781 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/078781
Method for designing chip package by re-using existing mask designs Mar 10, 2005 Issued
Array ( [id] => 5615355 [patent_doc_number] => 20060117285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Method for designing semiconductor integrated circuit, semiconductor integrated circuit and program for designing same' [patent_app_type] => utility [patent_app_number] => 11/066497 [patent_app_country] => US [patent_app_date] => 2005-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5625 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20060117285.pdf [firstpage_image] =>[orig_patent_app_number] => 11066497 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/066497
Method for designing semiconductor integrated circuit, semiconductor integrated circuit and program for designing same Feb 27, 2005 Issued
Array ( [id] => 5706757 [patent_doc_number] => 20060195805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Method and apparatus for quantifying the timing error induced by crosstalk between signal paths' [patent_app_type] => utility [patent_app_number] => 11/066587 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20060195805.pdf [firstpage_image] =>[orig_patent_app_number] => 11066587 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/066587
Method and apparatus for quantifying the timing error induced by crosstalk between signal paths Feb 24, 2005 Issued
Array ( [id] => 407403 [patent_doc_number] => 07290228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Hardware accelerator with a single partition for latches and combinational logic' [patent_app_type] => utility [patent_app_number] => 11/064727 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/290/07290228.pdf [firstpage_image] =>[orig_patent_app_number] => 11064727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064727
Hardware accelerator with a single partition for latches and combinational logic Feb 23, 2005 Issued
Array ( [id] => 5615359 [patent_doc_number] => 20060117289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Wiring method, program, and apparatus' [patent_app_type] => utility [patent_app_number] => 11/062617 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5332 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20060117289.pdf [firstpage_image] =>[orig_patent_app_number] => 11062617 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/062617
Wiring method, program, and apparatus Feb 21, 2005 Issued
Array ( [id] => 891042 [patent_doc_number] => 07353483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-01 [patent_title] => 'Element arrangement check device and printed circuit board design device' [patent_app_type] => utility [patent_app_number] => 10/556892 [patent_app_country] => US [patent_app_date] => 2005-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 8318 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/353/07353483.pdf [firstpage_image] =>[orig_patent_app_number] => 10556892 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/556892
Element arrangement check device and printed circuit board design device Feb 13, 2005 Issued
Array ( [id] => 7139942 [patent_doc_number] => 20050182587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Circuit quality evaluation method and apparatus, circuit quality evaluation program, and medium having the program recorded thereon' [patent_app_type] => utility [patent_app_number] => 11/052908 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 12448 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20050182587.pdf [firstpage_image] =>[orig_patent_app_number] => 11052908 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/052908
Circuit quality evaluation method and apparatus, circuit quality evaluation program, and medium having the program recorded thereon Feb 8, 2005 Abandoned
Array ( [id] => 898550 [patent_doc_number] => 07346866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Method and apparatus to generate circuit energy models with clock gating' [patent_app_type] => utility [patent_app_number] => 11/044597 [patent_app_country] => US [patent_app_date] => 2005-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2551 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/346/07346866.pdf [firstpage_image] =>[orig_patent_app_number] => 11044597 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/044597
Method and apparatus to generate circuit energy models with clock gating Jan 26, 2005 Issued
Array ( [id] => 7100734 [patent_doc_number] => 20050132315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Extendable method for revising patterned microelectronic conductor layer layouts' [patent_app_type] => utility [patent_app_number] => 11/044750 [patent_app_country] => US [patent_app_date] => 2005-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5200 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20050132315.pdf [firstpage_image] =>[orig_patent_app_number] => 11044750 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/044750
Extendable method for revising patterned microelectronic conductor layer layouts Jan 25, 2005 Abandoned
Array ( [id] => 5803744 [patent_doc_number] => 20060036984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Device and method for extracting parasitic capacitance of semiconductor circuit' [patent_app_type] => utility [patent_app_number] => 11/032187 [patent_app_country] => US [patent_app_date] => 2005-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3825 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20060036984.pdf [firstpage_image] =>[orig_patent_app_number] => 11032187 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/032187
Device and method for extracting parasitic capacitance of semiconductor circuit Jan 10, 2005 Abandoned
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