Search

Magid Y. Dimyan

Examiner (ID: 7023)

Most Active Art Unit
2825
Art Unit(s)
2851, 2825
Total Applications
684
Issued Applications
621
Pending Applications
9
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7088837 [patent_doc_number] => 20050008949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Methods of forming patterned reticles' [patent_app_type] => utility [patent_app_number] => 10/912029 [patent_app_country] => US [patent_app_date] => 2004-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9803 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20050008949.pdf [firstpage_image] =>[orig_patent_app_number] => 10912029 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/912029
Methods of forming patterned reticles Aug 3, 2004 Issued
Array ( [id] => 7088838 [patent_doc_number] => 20050008950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Methods of forming patterned reticles' [patent_app_type] => utility [patent_app_number] => 10/912030 [patent_app_country] => US [patent_app_date] => 2004-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9803 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20050008950.pdf [firstpage_image] =>[orig_patent_app_number] => 10912030 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/912030
Methods of forming patterned reticles Aug 3, 2004 Issued
Array ( [id] => 7088840 [patent_doc_number] => 20050008952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Methods of forming patterned reticles' [patent_app_type] => utility [patent_app_number] => 10/912256 [patent_app_country] => US [patent_app_date] => 2004-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9805 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20050008952.pdf [firstpage_image] =>[orig_patent_app_number] => 10912256 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/912256
Methods of forming patterned reticles Aug 3, 2004 Issued
Array ( [id] => 7088839 [patent_doc_number] => 20050008951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Methods of forming patterned reticles' [patent_app_type] => utility [patent_app_number] => 10/912031 [patent_app_country] => US [patent_app_date] => 2004-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9803 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20050008951.pdf [firstpage_image] =>[orig_patent_app_number] => 10912031 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/912031
Methods of forming patterned reticles Aug 3, 2004 Issued
Array ( [id] => 7088841 [patent_doc_number] => 20050008953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Methods of forming patterned reticles' [patent_app_type] => utility [patent_app_number] => 10/912510 [patent_app_country] => US [patent_app_date] => 2004-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9803 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20050008953.pdf [firstpage_image] =>[orig_patent_app_number] => 10912510 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/912510
Methods of forming patterned reticles Aug 3, 2004 Issued
Array ( [id] => 914830 [patent_doc_number] => 07331028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-12 [patent_title] => 'Engineering change order scenario manager' [patent_app_type] => utility [patent_app_number] => 10/902987 [patent_app_country] => US [patent_app_date] => 2004-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3789 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/331/07331028.pdf [firstpage_image] =>[orig_patent_app_number] => 10902987 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/902987
Engineering change order scenario manager Jul 29, 2004 Issued
Array ( [id] => 765660 [patent_doc_number] => 07017130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Method of verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/889497 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6126 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/017/07017130.pdf [firstpage_image] =>[orig_patent_app_number] => 10889497 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889497
Method of verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits Jul 11, 2004 Issued
Array ( [id] => 418407 [patent_doc_number] => 07281232 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-09 [patent_title] => 'Method and apparatus for automatically checking circuit layout routing' [patent_app_type] => utility [patent_app_number] => 10/875997 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11568 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/281/07281232.pdf [firstpage_image] =>[orig_patent_app_number] => 10875997 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875997
Method and apparatus for automatically checking circuit layout routing Jun 22, 2004 Issued
Array ( [id] => 7215866 [patent_doc_number] => 20050044518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Reservation of design elements in a parallel printed circuit board design environment' [patent_app_type] => utility [patent_app_number] => 10/870497 [patent_app_country] => US [patent_app_date] => 2004-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 10127 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20050044518.pdf [firstpage_image] =>[orig_patent_app_number] => 10870497 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/870497
Reservation of design elements in a parallel printed circuit board design environment Jun 17, 2004 Issued
Array ( [id] => 388870 [patent_doc_number] => 07305648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Distributed autorouting of conductive paths in printed circuit boards' [patent_app_type] => utility [patent_app_number] => 10/870072 [patent_app_country] => US [patent_app_date] => 2004-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 7988 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/305/07305648.pdf [firstpage_image] =>[orig_patent_app_number] => 10870072 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/870072
Distributed autorouting of conductive paths in printed circuit boards Jun 17, 2004 Issued
Array ( [id] => 7063561 [patent_doc_number] => 20050005254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Substrate noise analyzing method for semiconductor integrated circuit, semiconductor integrated circuit, and substrate noise analyzing device for semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/863327 [patent_app_country] => US [patent_app_date] => 2004-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3937 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20050005254.pdf [firstpage_image] =>[orig_patent_app_number] => 10863327 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/863327
Substrate noise analyzing method for semiconductor integrated circuit, semiconductor integrated circuit, and substrate noise analyzing device for semiconductor integrated circuit Jun 8, 2004 Abandoned
Array ( [id] => 7057509 [patent_doc_number] => 20050278684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Merging of infrastructure within a development environment' [patent_app_type] => utility [patent_app_number] => 10/858765 [patent_app_country] => US [patent_app_date] => 2004-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4070 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20050278684.pdf [firstpage_image] =>[orig_patent_app_number] => 10858765 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/858765
Merging of infrastructure within a development environment May 31, 2004 Issued
Array ( [id] => 466376 [patent_doc_number] => 07243322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-10 [patent_title] => 'Metastability injector for a circuit description' [patent_app_type] => utility [patent_app_number] => 10/859055 [patent_app_country] => US [patent_app_date] => 2004-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12172 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/243/07243322.pdf [firstpage_image] =>[orig_patent_app_number] => 10859055 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/859055
Metastability injector for a circuit description May 31, 2004 Issued
Array ( [id] => 7300775 [patent_doc_number] => 20040216073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Repeatable swizzling patterns for capacitive and inductive noise cancellation' [patent_app_type] => new [patent_app_number] => 10/852982 [patent_app_country] => US [patent_app_date] => 2004-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 13330 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20040216073.pdf [firstpage_image] =>[orig_patent_app_number] => 10852982 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/852982
Repeatable swizzling patterns for capacitive and inductive noise cancellation May 23, 2004 Abandoned
Array ( [id] => 7266919 [patent_doc_number] => 20040243967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Semiconductor design layout pattern formation method and graphic pattern formation unit' [patent_app_type] => new [patent_app_number] => 10/851294 [patent_app_country] => US [patent_app_date] => 2004-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5724 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20040243967.pdf [firstpage_image] =>[orig_patent_app_number] => 10851294 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/851294
Semiconductor design layout pattern formation method and graphic pattern formation unit May 23, 2004 Abandoned
Array ( [id] => 816704 [patent_doc_number] => 07415693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-19 [patent_title] => 'Method and apparatus for reducing synthesis runtime' [patent_app_type] => utility [patent_app_number] => 10/851355 [patent_app_country] => US [patent_app_date] => 2004-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4184 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/415/07415693.pdf [firstpage_image] =>[orig_patent_app_number] => 10851355 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/851355
Method and apparatus for reducing synthesis runtime May 20, 2004 Issued
Array ( [id] => 431566 [patent_doc_number] => 07269805 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-11 [patent_title] => 'Testing of an integrated circuit having an embedded processor' [patent_app_type] => utility [patent_app_number] => 10/836995 [patent_app_country] => US [patent_app_date] => 2004-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8141 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269805.pdf [firstpage_image] =>[orig_patent_app_number] => 10836995 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/836995
Testing of an integrated circuit having an embedded processor Apr 29, 2004 Issued
Array ( [id] => 435232 [patent_doc_number] => 07266793 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-04 [patent_title] => 'Extended model checking hardware verification' [patent_app_type] => utility [patent_app_number] => 10/806481 [patent_app_country] => US [patent_app_date] => 2004-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2949 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/266/07266793.pdf [firstpage_image] =>[orig_patent_app_number] => 10806481 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/806481
Extended model checking hardware verification Mar 21, 2004 Issued
Array ( [id] => 609704 [patent_doc_number] => 07155686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-26 [patent_title] => 'Placement and routing method to reduce Joule heating' [patent_app_type] => utility [patent_app_number] => 10/796430 [patent_app_country] => US [patent_app_date] => 2004-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 4910 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/155/07155686.pdf [firstpage_image] =>[orig_patent_app_number] => 10796430 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/796430
Placement and routing method to reduce Joule heating Mar 8, 2004 Issued
Array ( [id] => 6946953 [patent_doc_number] => 20050198597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Method and apparatus for performing generator-based verification' [patent_app_type] => utility [patent_app_number] => 10/796620 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7359 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20050198597.pdf [firstpage_image] =>[orig_patent_app_number] => 10796620 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/796620
Method and apparatus for performing generator-based verification Mar 7, 2004 Issued
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