Search

Magid Y. Dimyan

Examiner (ID: 7023)

Most Active Art Unit
2825
Art Unit(s)
2851, 2825
Total Applications
684
Issued Applications
621
Pending Applications
9
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 987882 [patent_doc_number] => 06925619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-02 [patent_title] => 'IC conductor capacitance estimation method' [patent_app_type] => utility [patent_app_number] => 10/443528 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 8000 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/925/06925619.pdf [firstpage_image] =>[orig_patent_app_number] => 10443528 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/443528
IC conductor capacitance estimation method May 20, 2003 Issued
Array ( [id] => 7321812 [patent_doc_number] => 20040225990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Removal of acute angles in a design layout' [patent_app_type] => new [patent_app_number] => 10/443315 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20040225990.pdf [firstpage_image] =>[orig_patent_app_number] => 10443315 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/443315
Removal of acute angles in a design layout May 20, 2003 Issued
Array ( [id] => 7437894 [patent_doc_number] => 20040230922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Practical method for hierarchical-preserving layout optimization of integrated circuit layout' [patent_app_type] => new [patent_app_number] => 10/438625 [patent_app_country] => US [patent_app_date] => 2003-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6714 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20040230922.pdf [firstpage_image] =>[orig_patent_app_number] => 10438625 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438625
Practical method for hierarchical-preserving layout optimization of integrated circuit layout May 14, 2003 Issued
Array ( [id] => 965764 [patent_doc_number] => 06951003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-27 [patent_title] => 'Placing cells of an IC design using partition preconditioning' [patent_app_type] => utility [patent_app_number] => 10/436578 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8581 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/951/06951003.pdf [firstpage_image] =>[orig_patent_app_number] => 10436578 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436578
Placing cells of an IC design using partition preconditioning May 11, 2003 Issued
Array ( [id] => 7615304 [patent_doc_number] => 06948143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-20 [patent_title] => 'Constrained optimization with linear constraints to remove overlap among cells of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/434737 [patent_app_country] => US [patent_app_date] => 2003-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5373 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/948/06948143.pdf [firstpage_image] =>[orig_patent_app_number] => 10434737 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/434737
Constrained optimization with linear constraints to remove overlap among cells of an integrated circuit May 8, 2003 Issued
Array ( [id] => 6810580 [patent_doc_number] => 20030200519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Method of simultaneously displaying schematic and timing data' [patent_app_type] => new [patent_app_number] => 10/431383 [patent_app_country] => US [patent_app_date] => 2003-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3605 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20030200519.pdf [firstpage_image] =>[orig_patent_app_number] => 10431383 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/431383
Method of simultaneously displaying schematic and timing data May 7, 2003 Issued
Array ( [id] => 7299002 [patent_doc_number] => 20040215436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Method, system and program product for implementing a read-only dial in a configuration database of a digital design' [patent_app_type] => new [patent_app_number] => 10/425080 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 39368 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20040215436.pdf [firstpage_image] =>[orig_patent_app_number] => 10425080 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/425080
Method, system and program product for implementing a read-only dial in a configuration database of a digital design Apr 27, 2003 Issued
Array ( [id] => 7300790 [patent_doc_number] => 20040216079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Method, system and program product for specifying a configuration of a digital system described by a hardware description language (HDL) model' [patent_app_type] => new [patent_app_number] => 10/425096 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 39350 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20040216079.pdf [firstpage_image] =>[orig_patent_app_number] => 10425096 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/425096
Method, system and program product for specifying a configuration of a digital system described by a hardware description language (HDL) model Apr 27, 2003 Issued
Array ( [id] => 713962 [patent_doc_number] => 07062745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Method, system and program product for specifying and using a dial having a default value to configure a digital system described by a hardware description language (HDL) model' [patent_app_type] => utility [patent_app_number] => 10/425079 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 46 [patent_no_of_words] => 38982 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/062/07062745.pdf [firstpage_image] =>[orig_patent_app_number] => 10425079 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/425079
Method, system and program product for specifying and using a dial having a default value to configure a digital system described by a hardware description language (HDL) model Apr 27, 2003 Issued
Array ( [id] => 676419 [patent_doc_number] => 07093205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'Method and apparatus for efficient semiconductor process evaluation' [patent_app_type] => utility [patent_app_number] => 10/412535 [patent_app_country] => US [patent_app_date] => 2003-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8193 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/093/07093205.pdf [firstpage_image] =>[orig_patent_app_number] => 10412535 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/412535
Method and apparatus for efficient semiconductor process evaluation Apr 9, 2003 Issued
Array ( [id] => 940603 [patent_doc_number] => 06973630 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-06 [patent_title] => 'System and method for reference-modeling a processor' [patent_app_type] => utility [patent_app_number] => 10/408387 [patent_app_country] => US [patent_app_date] => 2003-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4284 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/973/06973630.pdf [firstpage_image] =>[orig_patent_app_number] => 10408387 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/408387
System and method for reference-modeling a processor Apr 6, 2003 Issued
Array ( [id] => 989612 [patent_doc_number] => 06922817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-26 [patent_title] => 'System and method for achieving timing closure in fixed placed designs after implementing logic changes' [patent_app_type] => utility [patent_app_number] => 10/408205 [patent_app_country] => US [patent_app_date] => 2003-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2927 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/922/06922817.pdf [firstpage_image] =>[orig_patent_app_number] => 10408205 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/408205
System and method for achieving timing closure in fixed placed designs after implementing logic changes Apr 3, 2003 Issued
Array ( [id] => 7445555 [patent_doc_number] => 20040196069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'System and method for in-situ signal delay measurement for a microprocessor' [patent_app_type] => new [patent_app_number] => 10/407531 [patent_app_country] => US [patent_app_date] => 2003-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4709 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20040196069.pdf [firstpage_image] =>[orig_patent_app_number] => 10407531 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/407531
System and method for in-situ signal delay measurement for a microprocessor Apr 2, 2003 Issued
Array ( [id] => 7615300 [patent_doc_number] => 06948147 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-20 [patent_title] => 'Method and apparatus for configuring a programmable logic device using a master JTAG port' [patent_app_type] => utility [patent_app_number] => 10/407327 [patent_app_country] => US [patent_app_date] => 2003-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3482 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/948/06948147.pdf [firstpage_image] =>[orig_patent_app_number] => 10407327 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/407327
Method and apparatus for configuring a programmable logic device using a master JTAG port Apr 2, 2003 Issued
Array ( [id] => 749905 [patent_doc_number] => 07032208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Defect inspection apparatus' [patent_app_type] => utility [patent_app_number] => 10/395342 [patent_app_country] => US [patent_app_date] => 2003-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 4560 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/032/07032208.pdf [firstpage_image] =>[orig_patent_app_number] => 10395342 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/395342
Defect inspection apparatus Mar 24, 2003 Issued
Array ( [id] => 992896 [patent_doc_number] => 06920628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'Method and apparatus for defining mask patterns utilizing a spatial frequency doubling technique' [patent_app_type] => utility [patent_app_number] => 10/395887 [patent_app_country] => US [patent_app_date] => 2003-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 7249 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/920/06920628.pdf [firstpage_image] =>[orig_patent_app_number] => 10395887 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/395887
Method and apparatus for defining mask patterns utilizing a spatial frequency doubling technique Mar 24, 2003 Issued
Array ( [id] => 786231 [patent_doc_number] => 06993738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Method for allocating spare cells in auto-place-route blocks' [patent_app_type] => utility [patent_app_number] => 10/373989 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5409 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/993/06993738.pdf [firstpage_image] =>[orig_patent_app_number] => 10373989 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/373989
Method for allocating spare cells in auto-place-route blocks Feb 24, 2003 Issued
Array ( [id] => 6676892 [patent_doc_number] => 20030227032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Wiring design method of integrated circuit device, system thereof, and program product thereof' [patent_app_type] => new [patent_app_number] => 10/361679 [patent_app_country] => US [patent_app_date] => 2003-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6536 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20030227032.pdf [firstpage_image] =>[orig_patent_app_number] => 10361679 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/361679
Wiring design method of integrated circuit device, system thereof, and program product thereof Feb 10, 2003 Abandoned
Array ( [id] => 6989830 [patent_doc_number] => 20050088867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'System and method for design entry and synthesis in programmable logic devices' [patent_app_type] => utility [patent_app_number] => 10/353816 [patent_app_country] => US [patent_app_date] => 2003-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8835 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20050088867.pdf [firstpage_image] =>[orig_patent_app_number] => 10353816 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/353816
System and method for design entry and synthesis in programmable logic devices Jan 27, 2003 Issued
Array ( [id] => 6789092 [patent_doc_number] => 20030140331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Method for determining the ability to project images of integrated semiconductor circuits onto alternating phase masks' [patent_app_type] => new [patent_app_number] => 10/352735 [patent_app_country] => US [patent_app_date] => 2003-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5808 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20030140331.pdf [firstpage_image] =>[orig_patent_app_number] => 10352735 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/352735
Method for determining the ability to project images of integrated semiconductor circuits onto alternating phase masks Jan 26, 2003 Issued
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