Search

Magid Y. Dimyan

Examiner (ID: 9024)

Most Active Art Unit
2825
Art Unit(s)
2825, 2851
Total Applications
684
Issued Applications
621
Pending Applications
9
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9071305 [patent_doc_number] => 20130263061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'Global Landmark Method For Critical Dimension Uniformity Reconstruction' [patent_app_type] => utility [patent_app_number] => 13/878017 [patent_app_country] => US [patent_app_date] => 2011-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13698 [patent_no_of_claims] => 96 [patent_no_of_ind_claims] => 69 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13878017 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/878017
Global landmark method for critical dimension uniformity reconstruction Oct 4, 2011 Issued
Array ( [id] => 9276110 [patent_doc_number] => 08640058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'Method, program product and apparatus for model based geometry decomposition for use in a multiple exposure process' [patent_app_type] => utility [patent_app_number] => 13/244127 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8347 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13244127 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/244127
Method, program product and apparatus for model based geometry decomposition for use in a multiple exposure process Sep 22, 2011 Issued
Array ( [id] => 8873081 [patent_doc_number] => 08468470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Multi-patterning method' [patent_app_type] => utility [patent_app_number] => 13/238127 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 7672 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13238127 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/238127
Multi-patterning method Sep 20, 2011 Issued
Array ( [id] => 8722808 [patent_doc_number] => 20130074025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'POST TIMING LAYOUT MODIFICATION FOR PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 13/236977 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13236977 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/236977
Post timing layout modification for performance Sep 19, 2011 Issued
Array ( [id] => 9289518 [patent_doc_number] => 08645876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Methodology for performing post layer generation check' [patent_app_type] => utility [patent_app_number] => 13/234117 [patent_app_country] => US [patent_app_date] => 2011-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 7 [patent_no_of_words] => 3903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13234117 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/234117
Methodology for performing post layer generation check Sep 14, 2011 Issued
Array ( [id] => 9652384 [patent_doc_number] => 08806420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'In-grid on-device decoupling for BGA' [patent_app_type] => utility [patent_app_number] => 13/231587 [patent_app_country] => US [patent_app_date] => 2011-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1635 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13231587 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/231587
In-grid on-device decoupling for BGA Sep 12, 2011 Issued
Array ( [id] => 7671731 [patent_doc_number] => 20110321000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'TECHNIQUE FOR CREATING ANALYSIS MODEL AND TECHNIQUE FOR CREATING CIRCUIT BOARD MODEL' [patent_app_type] => utility [patent_app_number] => 13/226747 [patent_app_country] => US [patent_app_date] => 2011-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 18718 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13226747 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/226747
Technique for creating analysis model and technique for creating circuit board model Sep 6, 2011 Issued
Array ( [id] => 8878892 [patent_doc_number] => 08473877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Striping methodology for maskless lithography' [patent_app_type] => utility [patent_app_number] => 13/225617 [patent_app_country] => US [patent_app_date] => 2011-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13225617 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/225617
Striping methodology for maskless lithography Sep 5, 2011 Issued
Array ( [id] => 8935809 [patent_doc_number] => 08495531 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-23 [patent_title] => 'Method and system for providing an architecture for selecting and using components for an electronic design' [patent_app_type] => utility [patent_app_number] => 13/224107 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6390 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13224107 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/224107
Method and system for providing an architecture for selecting and using components for an electronic design Aug 31, 2011 Issued
Array ( [id] => 7654786 [patent_doc_number] => 20110304055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'Semiconductor integrated circuit with multi-cut via and automated layout method for the same' [patent_app_type] => utility [patent_app_number] => 13/137461 [patent_app_country] => US [patent_app_date] => 2011-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5361 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0304/20110304055.pdf [firstpage_image] =>[orig_patent_app_number] => 13137461 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/137461
Semiconductor integrated circuit with multi-cut via and automated layout method for the same Aug 16, 2011 Issued
Array ( [id] => 8971858 [patent_doc_number] => 08510688 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-13 [patent_title] => 'Method and apparatus for performing multiple stage physical synthesis' [patent_app_type] => utility [patent_app_number] => 13/136430 [patent_app_country] => US [patent_app_date] => 2011-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7305 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13136430 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/136430
Method and apparatus for performing multiple stage physical synthesis Jul 31, 2011 Issued
Array ( [id] => 7750641 [patent_doc_number] => 20120025403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'DESIGN APPARATUS OF SEMICONDUCTOR DEVICE, DESIGN METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/194607 [patent_app_country] => US [patent_app_date] => 2011-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7764 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20120025403.pdf [firstpage_image] =>[orig_patent_app_number] => 13194607 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/194607
DESIGN APPARATUS OF SEMICONDUCTOR DEVICE, DESIGN METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE Jul 28, 2011 Abandoned
Array ( [id] => 7588735 [patent_doc_number] => 20110283246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'Method and Apparatus for Merging EDA Coverage Logs of Coverage Data' [patent_app_type] => utility [patent_app_number] => 13/189314 [patent_app_country] => US [patent_app_date] => 2011-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9383 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20110283246.pdf [firstpage_image] =>[orig_patent_app_number] => 13189314 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/189314
Method and apparatus for merging EDA coverage logs of coverage data Jul 21, 2011 Issued
Array ( [id] => 8552412 [patent_doc_number] => 08327311 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-04 [patent_title] => 'Generating a simulation model of a circuit design' [patent_app_type] => utility [patent_app_number] => 13/188407 [patent_app_country] => US [patent_app_date] => 2011-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6465 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13188407 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/188407
Generating a simulation model of a circuit design Jul 20, 2011 Issued
Array ( [id] => 9593028 [patent_doc_number] => 08782594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Method for structuring a function plan into function plan sections' [patent_app_type] => utility [patent_app_number] => 13/809520 [patent_app_country] => US [patent_app_date] => 2011-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13809520 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/809520
Method for structuring a function plan into function plan sections May 23, 2011 Issued
Array ( [id] => 9665986 [patent_doc_number] => 08812997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Structural feature formation within an integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/067240 [patent_app_country] => US [patent_app_date] => 2011-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4644 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13067240 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/067240
Structural feature formation within an integrated circuit May 17, 2011 Issued
Array ( [id] => 6094367 [patent_doc_number] => 20110219343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'Converting Portions of a Software Program Executing on a Processing System to Hardware Descriptions' [patent_app_type] => utility [patent_app_number] => 13/110248 [patent_app_country] => US [patent_app_date] => 2011-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7633 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20110219343.pdf [firstpage_image] =>[orig_patent_app_number] => 13110248 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/110248
Converting portions of a software program executing on a processing system to hardware descriptions May 17, 2011 Issued
Array ( [id] => 7813544 [patent_doc_number] => 08136082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Method for testing integrated circuits' [patent_app_type] => utility [patent_app_number] => 13/102249 [patent_app_country] => US [patent_app_date] => 2011-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7328 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/136/08136082.pdf [firstpage_image] =>[orig_patent_app_number] => 13102249 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/102249
Method for testing integrated circuits May 5, 2011 Issued
Array ( [id] => 8810445 [patent_doc_number] => 08448112 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-21 [patent_title] => 'System, method, and computer program product for automatic power management verification' [patent_app_type] => utility [patent_app_number] => 13/082970 [patent_app_country] => US [patent_app_date] => 2011-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7383 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13082970 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/082970
System, method, and computer program product for automatic power management verification Apr 7, 2011 Issued
Array ( [id] => 7575584 [patent_doc_number] => 20110271240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'METHOD AND SYSTEM FOR COMPUTING FOURIER SERIES COEFFICIENTS FOR MASK LAYOUTS USING FFT' [patent_app_type] => utility [patent_app_number] => 13/082440 [patent_app_country] => US [patent_app_date] => 2011-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3728 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20110271240.pdf [firstpage_image] =>[orig_patent_app_number] => 13082440 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/082440
Method and system for computing fourier series coefficients for mask layouts using FFT Apr 7, 2011 Issued
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