Search

Magid Y. Dimyan

Examiner (ID: 9024)

Most Active Art Unit
2825
Art Unit(s)
2825, 2851
Total Applications
684
Issued Applications
621
Pending Applications
9
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8763399 [patent_doc_number] => 08423938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Wire spacing verification method, wire spacing verification apparatus, and computer-readable medium' [patent_app_type] => utility [patent_app_number] => 13/074330 [patent_app_country] => US [patent_app_date] => 2011-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 13683 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13074330 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/074330
Wire spacing verification method, wire spacing verification apparatus, and computer-readable medium Mar 28, 2011 Issued
Array ( [id] => 8655578 [patent_doc_number] => 08375346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-12 [patent_title] => 'Method and apparatus for laying out power wiring of semiconductor' [patent_app_type] => utility [patent_app_number] => 13/070500 [patent_app_country] => US [patent_app_date] => 2011-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5248 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13070500 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/070500
Method and apparatus for laying out power wiring of semiconductor Mar 23, 2011 Issued
Array ( [id] => 6191296 [patent_doc_number] => 20110173580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'Nonlinear Driver Model For Multi-Driver Systems' [patent_app_type] => utility [patent_app_number] => 13/052972 [patent_app_country] => US [patent_app_date] => 2011-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20110173580.pdf [firstpage_image] =>[orig_patent_app_number] => 13052972 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/052972
Nonlinear driver model for multi-driver systems Mar 20, 2011 Issued
Array ( [id] => 8805025 [patent_doc_number] => 08443309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Multifeature test pattern for optical proximity correction model verification' [patent_app_type] => utility [patent_app_number] => 13/040580 [patent_app_country] => US [patent_app_date] => 2011-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2964 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13040580 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/040580
Multifeature test pattern for optical proximity correction model verification Mar 3, 2011 Issued
Array ( [id] => 8382851 [patent_doc_number] => 20120226479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-06 [patent_title] => 'Method of Generating RC Technology File' [patent_app_type] => utility [patent_app_number] => 13/039730 [patent_app_country] => US [patent_app_date] => 2011-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3751 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13039730 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/039730
Method of generating RC technology file Mar 2, 2011 Issued
Array ( [id] => 8912510 [patent_doc_number] => 08484587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'Computational efficiency in photolithographic process simulation' [patent_app_type] => utility [patent_app_number] => 13/028508 [patent_app_country] => US [patent_app_date] => 2011-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 13400 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13028508 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/028508
Computational efficiency in photolithographic process simulation Feb 15, 2011 Issued
Array ( [id] => 9143592 [patent_doc_number] => 08584074 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-12 [patent_title] => 'Testing to prescribe state capture by, and state retrieval from scan registers' [patent_app_type] => utility [patent_app_number] => 12/987348 [patent_app_country] => US [patent_app_date] => 2011-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 9223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12987348 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/987348
Testing to prescribe state capture by, and state retrieval from scan registers Jan 9, 2011 Issued
Array ( [id] => 8667686 [patent_doc_number] => 08381159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Method of semiconductor integrated circuit, and computer readable medium' [patent_app_type] => utility [patent_app_number] => 12/978307 [patent_app_country] => US [patent_app_date] => 2010-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10411 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12978307 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/978307
Method of semiconductor integrated circuit, and computer readable medium Dec 22, 2010 Issued
Array ( [id] => 8540607 [patent_doc_number] => 08316335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Multistage, hybrid synthesis processing facilitating integrated circuit layout' [patent_app_type] => utility [patent_app_number] => 12/963677 [patent_app_country] => US [patent_app_date] => 2010-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12963677 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/963677
Multistage, hybrid synthesis processing facilitating integrated circuit layout Dec 8, 2010 Issued
Array ( [id] => 9236104 [patent_doc_number] => 08601420 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-03 [patent_title] => 'Equivalent waveform model for static timing analysis of integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/960387 [patent_app_country] => US [patent_app_date] => 2010-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 10033 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12960387 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/960387
Equivalent waveform model for static timing analysis of integrated circuit designs Dec 2, 2010 Issued
Array ( [id] => 8839380 [patent_doc_number] => 20130135008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'METHOD AND SYSTEM FOR A RUN-TIME RECONFIGURABLE COMPUTER ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/513277 [patent_app_country] => US [patent_app_date] => 2010-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 28894 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13513277 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/513277
Method and system for a run-time reconfigurable computer architecture Nov 30, 2010 Issued
Array ( [id] => 8223057 [patent_doc_number] => 20120137260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-31 [patent_title] => 'Virtual Photo-Mask Critical-Dimension Measurement' [patent_app_type] => utility [patent_app_number] => 12/955617 [patent_app_country] => US [patent_app_date] => 2010-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10049 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12955617 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/955617
Virtual photo-mask critical-dimension measurement Nov 28, 2010 Issued
Array ( [id] => 6021955 [patent_doc_number] => 20110050281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'METHOD AND SYSTEM FOR GROUPING LOGIC IN AN INTEGRATED CIRCUIT DESIGN TO MINIMIZE NUMBER OF TRANSISTORS AND NUMBER OF UNIQUE GEOMETRY PATTERNS' [patent_app_type] => utility [patent_app_number] => 12/938226 [patent_app_country] => US [patent_app_date] => 2010-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5644 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20110050281.pdf [firstpage_image] =>[orig_patent_app_number] => 12938226 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/938226
METHOD AND SYSTEM FOR GROUPING LOGIC IN AN INTEGRATED CIRCUIT DESIGN TO MINIMIZE NUMBER OF TRANSISTORS AND NUMBER OF UNIQUE GEOMETRY PATTERNS Nov 1, 2010 Abandoned
Array ( [id] => 6194596 [patent_doc_number] => 20110026350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'Resettable Memory Apparatuses and Design' [patent_app_type] => utility [patent_app_number] => 12/902089 [patent_app_country] => US [patent_app_date] => 2010-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11519 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20110026350.pdf [firstpage_image] =>[orig_patent_app_number] => 12902089 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/902089
Resettable memory apparatuses and design Oct 10, 2010 Issued
Array ( [id] => 8094629 [patent_doc_number] => 20120082923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => ' PHOTOMASK THROUGHPUT BY REDUCING EXPOSURE SHOT COUNT FOR NON-CRITICAL ELEMENTS' [patent_app_type] => utility [patent_app_number] => 12/896947 [patent_app_country] => US [patent_app_date] => 2010-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20120082923.pdf [firstpage_image] =>[orig_patent_app_number] => 12896947 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/896947
Photomask throughput by reducing exposure shot count for non-critical elements Oct 3, 2010 Issued
Array ( [id] => 8946075 [patent_doc_number] => 08499262 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-30 [patent_title] => 'Method and apparatus for implementing a parameterizable filter block with an electronic design automation tool' [patent_app_type] => utility [patent_app_number] => 12/807959 [patent_app_country] => US [patent_app_date] => 2010-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 12491 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12807959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/807959
Method and apparatus for implementing a parameterizable filter block with an electronic design automation tool Sep 16, 2010 Issued
Array ( [id] => 8837330 [patent_doc_number] => 08453100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Circuit analysis using transverse buckets' [patent_app_type] => utility [patent_app_number] => 12/873554 [patent_app_country] => US [patent_app_date] => 2010-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 9032 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12873554 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/873554
Circuit analysis using transverse buckets Aug 31, 2010 Issued
Array ( [id] => 6397389 [patent_doc_number] => 20100318947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'METHOD FOR THE DEFINITION OF A LIBRARY OF APPLICATION-DOMAIN-SPECIFIC LOGIC CELLS' [patent_app_type] => utility [patent_app_number] => 12/862439 [patent_app_country] => US [patent_app_date] => 2010-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5797 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0318/20100318947.pdf [firstpage_image] =>[orig_patent_app_number] => 12862439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/862439
Method for the definition of a library of application-domain-specific logic cells Aug 23, 2010 Issued
Array ( [id] => 6057678 [patent_doc_number] => 20110113395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'Method, Electronic Design Automation Tool, Computer Program Product, and Data Processing Program for Creating a Layout for Design Representation of an Electronic Circuit and Corresponding Port for an Electronic Circuit' [patent_app_type] => utility [patent_app_number] => 12/861087 [patent_app_country] => US [patent_app_date] => 2010-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5249 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20110113395.pdf [firstpage_image] =>[orig_patent_app_number] => 12861087 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/861087
Method, electronic design automation tool, computer program product, and data processing program for creating a layout for design representation of an electronic circuit and corresponding port for an electronic circuit Aug 22, 2010 Issued
Array ( [id] => 9431157 [patent_doc_number] => 08707244 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-22 [patent_title] => 'Methods and systems for performing signal activity extraction' [patent_app_type] => utility [patent_app_number] => 12/860827 [patent_app_country] => US [patent_app_date] => 2010-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7670 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12860827 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/860827
Methods and systems for performing signal activity extraction Aug 19, 2010 Issued
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