Magid Y. Dimyan

Array ( [id] => 8536226 [patent_doc_number] => 08312393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Variable overlap method and device for stitching together lithographic stripes' [patent_app_type] => utility [patent_app_number] => 12/718900 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5490 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12718900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8536244 [patent_doc_number] => 08312410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Parameterized cell caching in electronic design automation' [patent_app_type] => utility [patent_app_number] => 12/718850 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6554 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12718850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8461012 [patent_doc_number] => 08296698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'High-speed SRAM' [patent_app_type] => utility [patent_app_number] => 12/712590 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3721 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12712590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8561932 [patent_doc_number] => 08336003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-18 [patent_title] => 'Method for designing optical lithography masks for directed self-assembly' [patent_app_type] => utility [patent_app_number] => 12/708570 [patent_app_country] => US [patent_app_date] => 2010-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 37 [patent_no_of_words] => 11654 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12708570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8401533 [patent_doc_number] => 08271929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-18 [patent_title] => 'Method for clock load alignment during standard cell optimization' [patent_app_type] => utility [patent_app_number] => 12/708700 [patent_app_country] => US [patent_app_date] => 2010-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7061 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12708700 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7683150 [patent_doc_number] => 20100241261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'PATTERN GENERATING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 12/705640 [patent_app_country] => US [patent_app_date] => 2010-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20100241261.pdf [firstpage_image] =>[orig_patent_app_number] => 12705640 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6587707 [patent_doc_number] => 20100235798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'METHOD FOR PREDICTING AND DEBUGGING EMI CHARACTERISTICS IN IC SYSTEM AND RELATED MACHINE-READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/703770 [patent_app_country] => US [patent_app_date] => 2010-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20100235798.pdf [firstpage_image] =>[orig_patent_app_number] => 12703770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6241421 [patent_doc_number] => 20100269076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'TEST PATTERN GENERATION APPARATUS, TEST PATTERN GENERATION METHOD, AND MEDIUM STORING TEST PATTERN GENERATION PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/696280 [patent_app_country] => US [patent_app_date] => 2010-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20100269076.pdf [firstpage_image] =>[orig_patent_app_number] => 12696280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6302850 [patent_doc_number] => 20100162193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'METHOD AND PROCESS FOR DESIGN OF INTEGRATED CIRCUITS USING REGULAR GEOMETRY PATTERNS TO OBTAIN GEOMETRICALLY CONSISTENT COMPONENT FEATURES' [patent_app_type] => utility [patent_app_number] => 12/697161 [patent_app_country] => US [patent_app_date] => 2010-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4057 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20100162193.pdf [firstpage_image] =>[orig_patent_app_number] => 12697161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5960937 [patent_doc_number] => 20110185324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'METHOD AND APPARATUS FOR CALIBRATING A PHOTOLITHOGRAPHY PROCESS MODEL BY USING A PROCESS WINDOW PARAMETER' [patent_app_type] => utility [patent_app_number] => 12/695530 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5000 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20110185324.pdf [firstpage_image] =>[orig_patent_app_number] => 12695530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5956594 [patent_doc_number] => 20110181331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'INTEGRATED CIRCUIT WITH LEAKAGE REDUCTION IN STATIC NETS' [patent_app_type] => utility [patent_app_number] => 12/692640 [patent_app_country] => US [patent_app_date] => 2010-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4302 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20110181331.pdf [firstpage_image] =>[orig_patent_app_number] => 12692640 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7706517 [patent_doc_number] => 08091047 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-03 [patent_title] => 'System and method for implementing image-based design rules' [patent_app_type] => utility [patent_app_number] => 12/644742 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 13083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/091/08091047.pdf [firstpage_image] =>[orig_patent_app_number] => 12644742 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9218563 [patent_doc_number] => 08631373 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-14 [patent_title] => 'Yield analysis with situations' [patent_app_type] => utility [patent_app_number] => 12/645173 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7706 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12645173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8633004 [patent_doc_number] => 08365103 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-29 [patent_title] => 'System and method for implementing image-based design rules' [patent_app_type] => utility [patent_app_number] => 12/644647 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 13086 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12644647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8552400 [patent_doc_number] => 08327299 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-04 [patent_title] => 'System and method for implementing image-based design rules' [patent_app_type] => utility [patent_app_number] => 12/644789 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 13084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12644789 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9029817 [patent_doc_number] => 08539415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Reconfigurable circuit, its design method, and design apparatus' [patent_app_type] => utility [patent_app_number] => 12/635347 [patent_app_country] => US [patent_app_date] => 2009-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6131 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12635347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6217623 [patent_doc_number] => 20110138157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'CONVOLUTION COMPUTATION FOR MANY-CORE PROCESSOR ARCHITECTURES' [patent_app_type] => utility [patent_app_number] => 12/631167 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8630 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20110138157.pdf [firstpage_image] =>[orig_patent_app_number] => 12631167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 28604 [patent_doc_number] => 07797667 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-14 [patent_title] => 'Hardware acceleration of functional factoring' [patent_app_type] => utility [patent_app_number] => 12/628230 [patent_app_country] => US [patent_app_date] => 2009-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 8194 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797667.pdf [firstpage_image] =>[orig_patent_app_number] => 12628230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7671726 [patent_doc_number] => 20110320995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'Noise Analysis Designing Method' [patent_app_type] => utility [patent_app_number] => 13/145694 [patent_app_country] => US [patent_app_date] => 2009-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4520 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13145694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8220445 [patent_doc_number] => 08196080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Method and system for routing' [patent_app_type] => utility [patent_app_number] => 12/611581 [patent_app_country] => US [patent_app_date] => 2009-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 45 [patent_no_of_words] => 8035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/196/08196080.pdf [firstpage_image] =>[orig_patent_app_number] => 12611581 [rel_patent_id] =>[rel_patent_doc_number] =>)