Search

Magid Y. Dimyan

Examiner (ID: 9024)

Most Active Art Unit
2825
Art Unit(s)
2825, 2851
Total Applications
684
Issued Applications
621
Pending Applications
9
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6040774 [patent_doc_number] => 20110093823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'SEMICONDUCTOR INTER-FIELD DOSE CORRECTION' [patent_app_type] => utility [patent_app_number] => 12/580347 [patent_app_country] => US [patent_app_date] => 2009-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20110093823.pdf [firstpage_image] =>[orig_patent_app_number] => 12580347 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/580347
Semiconductor inter-field dose correction Oct 15, 2009 Issued
Array ( [id] => 8461028 [patent_doc_number] => 08296714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'System and method for checking analog circuit with digital checker' [patent_app_type] => utility [patent_app_number] => 12/580717 [patent_app_country] => US [patent_app_date] => 2009-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7643 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12580717 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/580717
System and method for checking analog circuit with digital checker Oct 15, 2009 Issued
Array ( [id] => 7683913 [patent_doc_number] => 20100122228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'METHOD AND SYSTEM FOR CONDUCTING DESIGN EXPLORATIONS OF AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/577402 [patent_app_country] => US [patent_app_date] => 2009-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4139 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20100122228.pdf [firstpage_image] =>[orig_patent_app_number] => 12577402 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/577402
Method and system for conducting design explorations of an integrated circuit Oct 11, 2009 Issued
Array ( [id] => 8331725 [patent_doc_number] => 08239802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Robust method for integration of bump cells in semiconductor device design' [patent_app_type] => utility [patent_app_number] => 12/575147 [patent_app_country] => US [patent_app_date] => 2009-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4207 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12575147 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/575147
Robust method for integration of bump cells in semiconductor device design Oct 6, 2009 Issued
Array ( [id] => 10015440 [patent_doc_number] => 09058454 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-16 [patent_title] => 'Method and apparatus to reduce power segmentation overhead within an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/570637 [patent_app_country] => US [patent_app_date] => 2009-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5855 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12570637 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/570637
Method and apparatus to reduce power segmentation overhead within an integrated circuit Sep 29, 2009 Issued
Array ( [id] => 7780277 [patent_doc_number] => 08122414 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-21 [patent_title] => 'Placeholder-based design flow for creating circuit designs for integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/569497 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6957 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/122/08122414.pdf [firstpage_image] =>[orig_patent_app_number] => 12569497 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/569497
Placeholder-based design flow for creating circuit designs for integrated circuits Sep 28, 2009 Issued
Array ( [id] => 8033857 [patent_doc_number] => 08146023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-27 [patent_title] => 'Integrated circuit fabrication process convergence' [patent_app_type] => utility [patent_app_number] => 12/565787 [patent_app_country] => US [patent_app_date] => 2009-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3666 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/146/08146023.pdf [firstpage_image] =>[orig_patent_app_number] => 12565787 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/565787
Integrated circuit fabrication process convergence Sep 23, 2009 Issued
Array ( [id] => 9023651 [patent_doc_number] => 08533650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Annotation management for hierarchical designs of integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/562067 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 6183 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12562067 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/562067
Annotation management for hierarchical designs of integrated circuits Sep 16, 2009 Issued
Array ( [id] => 7993403 [patent_doc_number] => 08079010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Wiring information generating apparatus, method and program' [patent_app_type] => utility [patent_app_number] => 12/559837 [patent_app_country] => US [patent_app_date] => 2009-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 35 [patent_no_of_words] => 9595 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/079/08079010.pdf [firstpage_image] =>[orig_patent_app_number] => 12559837 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/559837
Wiring information generating apparatus, method and program Sep 14, 2009 Issued
Array ( [id] => 8343238 [patent_doc_number] => 08245178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Method for multi-cycle clock gating' [patent_app_type] => utility [patent_app_number] => 12/501566 [patent_app_country] => US [patent_app_date] => 2009-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4176 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12501566 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/501566
Method for multi-cycle clock gating Jul 12, 2009 Issued
Array ( [id] => 4602992 [patent_doc_number] => 07979837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-12 [patent_title] => 'Calculating distortion summaries for circuit distortion analysis' [patent_app_type] => utility [patent_app_number] => 12/484865 [patent_app_country] => US [patent_app_date] => 2009-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/979/07979837.pdf [firstpage_image] =>[orig_patent_app_number] => 12484865 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/484865
Calculating distortion summaries for circuit distortion analysis Jun 14, 2009 Issued
Array ( [id] => 5305914 [patent_doc_number] => 20090300566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'Hierarchical Partitioning' [patent_app_type] => utility [patent_app_number] => 12/471343 [patent_app_country] => US [patent_app_date] => 2009-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6608 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20090300566.pdf [firstpage_image] =>[orig_patent_app_number] => 12471343 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/471343
Hierarchical Partitioning May 21, 2009 Abandoned
Array ( [id] => 5305904 [patent_doc_number] => 20090300556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'Hierarchical Partitioning' [patent_app_type] => utility [patent_app_number] => 12/471344 [patent_app_country] => US [patent_app_date] => 2009-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6608 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20090300556.pdf [firstpage_image] =>[orig_patent_app_number] => 12471344 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/471344
Hierarchical partitioning May 21, 2009 Issued
Array ( [id] => 158075 [patent_doc_number] => 07685559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Step-walk relaxation method for global optimization of masks' [patent_app_type] => utility [patent_app_number] => 12/416312 [patent_app_country] => US [patent_app_date] => 2009-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10814 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685559.pdf [firstpage_image] =>[orig_patent_app_number] => 12416312 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/416312
Step-walk relaxation method for global optimization of masks Mar 31, 2009 Issued
Array ( [id] => 6566369 [patent_doc_number] => 20100017765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'MONITOR POSITION DETERMINING APPARATUS AND MONITOR POSITION DETERMINING METHOD' [patent_app_type] => utility [patent_app_number] => 12/409187 [patent_app_country] => US [patent_app_date] => 2009-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9892 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20100017765.pdf [firstpage_image] =>[orig_patent_app_number] => 12409187 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/409187
Monitor position determining apparatus and monitor position determining method Mar 22, 2009 Issued
Array ( [id] => 5473727 [patent_doc_number] => 20090246893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING PROCESS EVALUATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/407987 [patent_app_country] => US [patent_app_date] => 2009-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5559 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20090246893.pdf [firstpage_image] =>[orig_patent_app_number] => 12407987 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/407987
Semiconductor integrated circuit manufacturing process evaluation method Mar 19, 2009 Issued
Array ( [id] => 8805038 [patent_doc_number] => 08443322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Using layout enumeration to facilitate integrated circuit development' [patent_app_type] => utility [patent_app_number] => 12/406996 [patent_app_country] => US [patent_app_date] => 2009-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4713 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12406996 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/406996
Using layout enumeration to facilitate integrated circuit development Mar 18, 2009 Issued
Array ( [id] => 5571491 [patent_doc_number] => 20090254870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-08 [patent_title] => 'Automatic transistor arrangement device to arrange serially connected transistors, and method thereof' [patent_app_type] => utility [patent_app_number] => 12/382547 [patent_app_country] => US [patent_app_date] => 2009-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4100 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20090254870.pdf [firstpage_image] =>[orig_patent_app_number] => 12382547 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/382547
Automatic transistor arrangement device to arrange serially connected transistors, and method thereof Mar 17, 2009 Abandoned
Array ( [id] => 7686273 [patent_doc_number] => 20090178018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'PRE-BIAS OPTICAL PROXIMITY CORRECTION' [patent_app_type] => utility [patent_app_number] => 12/406820 [patent_app_country] => US [patent_app_date] => 2009-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 2719 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20090178018.pdf [firstpage_image] =>[orig_patent_app_number] => 12406820 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/406820
Pre-bias optical proximity correction Mar 17, 2009 Issued
Array ( [id] => 8703966 [patent_doc_number] => 08397203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Planar manufacturing drawing production support device, planar manufacturing drawing production support method, planar manufacturing drawing production support program and branch angle design support device' [patent_app_type] => utility [patent_app_number] => 12/735917 [patent_app_country] => US [patent_app_date] => 2009-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 13758 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12735917 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/735917
Planar manufacturing drawing production support device, planar manufacturing drawing production support method, planar manufacturing drawing production support program and branch angle design support device Feb 24, 2009 Issued
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