Mahelet Shiberou

Array ( [id] => 20265777 [patent_doc_number] => 12436768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Universal pointers for data exchange in a computer system having independent processors [patent_app_type] => utility [patent_app_number] => 18/148701 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18213798 [patent_doc_number] => 20230060064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => APPARATUS INCLUDING PARALLEL PIPELINES AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/979679 [patent_app_country] => US [patent_app_date] => 2022-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17979679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18312874 [patent_doc_number] => 20230116774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => LOAD REDUCED NONVOLATILE MEMORY INTERFACE [patent_app_type] => utility [patent_app_number] => 17/971201 [patent_app_country] => US [patent_app_date] => 2022-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17971201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18622291 [patent_doc_number] => 11755332 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-12 [patent_title] => Performance benchmarking-based selection of processor for generating graphic primitives [patent_app_type] => utility [patent_app_number] => 17/962277 [patent_app_country] => US [patent_app_date] => 2022-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5437 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17962277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19085494 [patent_doc_number] => 20240112295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => SHARED LOCAL REGISTERS FOR THREAD TEAM PROCESSING [patent_app_type] => utility [patent_app_number] => 17/958216 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 47729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958216 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19069472 [patent_doc_number] => 20240103898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => INPUT-OUTPUT PROCESSING IN SOFTWARE-DEFINED STORAGE SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/954886 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18765650 [patent_doc_number] => 11816048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Chip card socket communication [patent_app_type] => utility [patent_app_number] => 17/953874 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10201 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953874 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19069442 [patent_doc_number] => 20240103868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => Virtual Idle Loops [patent_app_type] => utility [patent_app_number] => 17/953486 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19144416 [patent_doc_number] => 20240143329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => Apparatus, Device, Method, and Computer Program for Extending Instructions Supported by a Processor [patent_app_type] => utility [patent_app_number] => 17/934580 [patent_app_country] => US [patent_app_date] => 2022-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9456 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19144416 [patent_doc_number] => 20240143329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => Apparatus, Device, Method, and Computer Program for Extending Instructions Supported by a Processor [patent_app_type] => utility [patent_app_number] => 17/934580 [patent_app_country] => US [patent_app_date] => 2022-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9456 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18284850 [patent_doc_number] => 20230100322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => METHOD AND SYSTEM TO MONITOR DRIFT IN A VIRTUAL DEVELOPMENTAL ENVIRONMENT OF ABSTRACTED CONTAINERIZED APPLICATIONS [patent_app_type] => utility [patent_app_number] => 17/949114 [patent_app_country] => US [patent_app_date] => 2022-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18140576 [patent_doc_number] => 20230014415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => REDUCING TRANSACTIONS DROP IN REMOTE DIRECT MEMORY ACCESS SYSTEM [patent_app_type] => utility [patent_app_number] => 17/947826 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17947826 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19006022 [patent_doc_number] => 20240070093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => Asymmetric Read-Write Sequence for Interconnected Dies [patent_app_type] => utility [patent_app_number] => 17/823443 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11791 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -40 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18253245 [patent_doc_number] => 20230080284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => DEVICES USING CHIPLET BASED STORAGE ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 17/898975 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19538205 [patent_doc_number] => 12130758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Data transmission power optimization [patent_app_type] => utility [patent_app_number] => 17/821935 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4975 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17821935 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19949939 [patent_doc_number] => 12321301 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-03 [patent_title] => Low-latency packet processing for network device [patent_app_type] => utility [patent_app_number] => 17/891200 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 8244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18592117 [patent_doc_number] => 11741015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Fault buffer for tracking page faults in unified virtual memory system [patent_app_type] => utility [patent_app_number] => 17/820870 [patent_app_country] => US [patent_app_date] => 2022-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13075 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17820870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20000829 [patent_doc_number] => 20250139051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => GLOBALS BLOCKS IN REPLICATED BLOCK ARRAYS [patent_app_type] => utility [patent_app_number] => 18/683636 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18683636 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18022883 [patent_doc_number] => 20220374382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => METHOD AND APPARATUS FOR EXTENDING I3C CAPABILITY ACROSS MULTIPLE PLATFORMS AND DEVICES OVER USB-C CONNECTION [patent_app_type] => utility [patent_app_number] => 17/882462 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17882462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18644714 [patent_doc_number] => 11768782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Data bus duty cycle distortion compensation [patent_app_type] => utility [patent_app_number] => 17/880226 [patent_app_country] => US [patent_app_date] => 2022-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17880226 [rel_patent_id] =>[rel_patent_doc_number] =>)