Search

Maliheh Malek

Examiner (ID: 5440, Phone: (571)270-1874 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
776
Issued Applications
577
Pending Applications
69
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18223462 [patent_doc_number] => 20230062456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND DISPLAY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/982164 [patent_app_country] => US [patent_app_date] => 2022-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17982164 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/982164
Semiconductor device, method of fabricating the same, and display device including the same Nov 6, 2022 Issued
Array ( [id] => 18379941 [patent_doc_number] => 20230155030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => ARRAY SUBSTRATE AND DISPLAY DEVICE INCLUDING THEREOF [patent_app_type] => utility [patent_app_number] => 17/977978 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17977978 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/977978
Array substrate and display device including thereof Oct 30, 2022 Issued
Array ( [id] => 20597949 [patent_doc_number] => 12581686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Metal oxide semiconductor devices and integration methods [patent_app_type] => utility [patent_app_number] => 18/046531 [patent_app_country] => US [patent_app_date] => 2022-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18046531 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/046531
Metal oxide semiconductor devices and integration methods Oct 13, 2022 Issued
Array ( [id] => 20540241 [patent_doc_number] => 12557328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Vertical-transport field-effect transistor with backside source/drain connections [patent_app_type] => utility [patent_app_number] => 17/936434 [patent_app_country] => US [patent_app_date] => 2022-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 10100 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17936434 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/936434
Vertical-transport field-effect transistor with backside source/drain connections Sep 28, 2022 Issued
Array ( [id] => 19055060 [patent_doc_number] => 20240097029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => FIELD EFFECT TRANSISTOR WITH ADJUSTABLE EFFECTIVE GATE LENGTH [patent_app_type] => utility [patent_app_number] => 17/933304 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17933304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/933304
Field effect transistor with adjustable effective gate length Sep 18, 2022 Issued
Array ( [id] => 18125027 [patent_doc_number] => 20230010642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/932593 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932593 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932593
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME Sep 14, 2022 Abandoned
Array ( [id] => 19023281 [patent_doc_number] => 20240079452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => VERTICAL TRANSISTOR STRUCTURES WITH OFFSET SPACERS [patent_app_type] => utility [patent_app_number] => 17/939617 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939617 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/939617
VERTICAL TRANSISTOR STRUCTURES WITH OFFSET SPACERS Sep 6, 2022 Abandoned
Array ( [id] => 20792750 [patent_doc_number] => 12666682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Vertical transport transistor devices with back side interconnects [patent_app_type] => utility [patent_app_number] => 17/901133 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 37 [patent_no_of_words] => 4052 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/901133
Vertical transport transistor devices with back side interconnects Aug 31, 2022 Issued
Array ( [id] => 19023322 [patent_doc_number] => 20240079493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/823985 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823985 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/823985
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Aug 31, 2022 Issued
Array ( [id] => 20705679 [patent_doc_number] => 12628406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Performance optimization by sizing gates and source/drain contacts differently for different transistors [patent_app_type] => utility [patent_app_number] => 17/900639 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 31 [patent_no_of_words] => 7821 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17900639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/900639
Performance optimization by sizing gates and source/drain contacts differently for different transistors Aug 30, 2022 Issued
Array ( [id] => 18359838 [patent_doc_number] => 20230141429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/883683 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883683
Semiconductor device including oxide semiconductor layer Aug 8, 2022 Issued
Array ( [id] => 18222144 [patent_doc_number] => 20230061138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/816749 [patent_app_country] => US [patent_app_date] => 2022-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -37 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17816749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/816749
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FORMING THE SAME Aug 1, 2022 Pending
Array ( [id] => 19502091 [patent_doc_number] => 20240341109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => DISPLAY APPARATUS AND MANUFACTURING METHOD OF DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/292122 [patent_app_country] => US [patent_app_date] => 2022-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 53762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18292122 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/292122
DISPLAY APPARATUS AND MANUFACTURING METHOD OF DISPLAY APPARATUS Aug 1, 2022 Pending
Array ( [id] => 18008994 [patent_doc_number] => 20220367761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => LIGHT EMITTING DIODE PACKAGE [patent_app_type] => utility [patent_app_number] => 17/875358 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875358 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/875358
LIGHT EMITTING DIODE PACKAGE Jul 26, 2022 Pending
Array ( [id] => 18008503 [patent_doc_number] => 20220367270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => SELF-ALIGNED CONTACT AND CONTACT OVER ACTIVE GATE STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/873547 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873547 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873547
SELF-ALIGNED CONTACT AND CONTACT OVER ACTIVE GATE STRUCTURES Jul 25, 2022 Abandoned
Array ( [id] => 18040427 [patent_doc_number] => 20220384644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => Semiconductor Device [patent_app_type] => utility [patent_app_number] => 17/814683 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814683
Semiconductor device Jul 24, 2022 Issued
Array ( [id] => 18906124 [patent_doc_number] => 20240021609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => VTFET WITH REDUCED PARASITIC CAPACITANCE [patent_app_type] => utility [patent_app_number] => 17/812744 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17812744 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/812744
VTFET with reduced parasitic capacitance Jul 14, 2022 Issued
Array ( [id] => 20375262 [patent_doc_number] => 12482706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Semiconductor structure that includes self-aligned contact plugs and methods for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/862710 [patent_app_country] => US [patent_app_date] => 2022-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4209 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17862710 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/862710
Semiconductor structure that includes self-aligned contact plugs and methods for manufacturing the same Jul 11, 2022 Issued
Array ( [id] => 17949585 [patent_doc_number] => 20220336604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR STRUCTURE FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/810814 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810814 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/810814
Method for forming semiconductor structure for memory device Jul 4, 2022 Issued
Array ( [id] => 20496674 [patent_doc_number] => 12538565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Self-aligned bottom spacer [patent_app_type] => utility [patent_app_number] => 17/810652 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 1091 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810652 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/810652
Self-aligned bottom spacer Jul 4, 2022 Issued
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