Search

Mamadou L. Diallo

Examiner (ID: 18306)

Most Active Art Unit
2895
Art Unit(s)
3648, 2897, 2819, 2895, 2811, 4174
Total Applications
1724
Issued Applications
1539
Pending Applications
108
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20347558 [patent_doc_number] => 12471296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => High bandwidth memory stack with side edge interconnection and 3D IC structure with the same [patent_app_type] => utility [patent_app_number] => 19/062566 [patent_app_country] => US [patent_app_date] => 2025-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 5363 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19062566 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/062566
High bandwidth memory stack with side edge interconnection and 3D IC structure with the same Feb 24, 2025 Issued
Array ( [id] => 20347558 [patent_doc_number] => 12471296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => High bandwidth memory stack with side edge interconnection and 3D IC structure with the same [patent_app_type] => utility [patent_app_number] => 19/062566 [patent_app_country] => US [patent_app_date] => 2025-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 5363 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19062566 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/062566
High bandwidth memory stack with side edge interconnection and 3D IC structure with the same Feb 24, 2025 Issued
Array ( [id] => 20104653 [patent_doc_number] => 20250234589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => THIN FILM SEMICONDUCTOR SWITCHING DEVICE [patent_app_type] => utility [patent_app_number] => 19/060198 [patent_app_country] => US [patent_app_date] => 2025-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19060198 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/060198
Thin film semiconductor switching device Feb 20, 2025 Issued
Array ( [id] => 20004603 [patent_doc_number] => 20250142825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => 3D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 19/004160 [patent_app_country] => US [patent_app_date] => 2024-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19004160 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/004160
3D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY CELLS Dec 26, 2024 Pending
Array ( [id] => 20191192 [patent_doc_number] => 12402330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => 3D memory devices and structures with memory arrays and metal layers [patent_app_type] => utility [patent_app_number] => 18/963630 [patent_app_country] => US [patent_app_date] => 2024-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 148 [patent_no_of_words] => 36710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18963630 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/963630
3D memory devices and structures with memory arrays and metal layers Nov 27, 2024 Issued
Array ( [id] => 20082622 [patent_doc_number] => 12356724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Double-sided integrated circuit die and integrated circuit package including the same [patent_app_type] => utility [patent_app_number] => 18/900415 [patent_app_country] => US [patent_app_date] => 2024-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1120 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18900415 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/900415
Double-sided integrated circuit die and integrated circuit package including the same Sep 26, 2024 Issued
Array ( [id] => 20082622 [patent_doc_number] => 12356724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Double-sided integrated circuit die and integrated circuit package including the same [patent_app_type] => utility [patent_app_number] => 18/900415 [patent_app_country] => US [patent_app_date] => 2024-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1120 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18900415 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/900415
Double-sided integrated circuit die and integrated circuit package including the same Sep 26, 2024 Issued
Array ( [id] => 19688161 [patent_doc_number] => 20250006706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => Backside Integrated Voltage Regulator For Integrated Circuits [patent_app_type] => utility [patent_app_number] => 18/823093 [patent_app_country] => US [patent_app_date] => 2024-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18823093 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/823093
Backside integrated voltage regulator for integrated circuits Sep 2, 2024 Issued
Array ( [id] => 20153367 [patent_doc_number] => 20250253205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => EMBEDDED COOLING SYSTEMS FOR ADVANCED DEVICE PACKAGING AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/787506 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18787506 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/787506
EMBEDDED COOLING SYSTEMS FOR ADVANCED DEVICE PACKAGING AND METHODS OF MANUFACTURING THE SAME Jul 28, 2024 Pending
Array ( [id] => 19560004 [patent_doc_number] => 20240371796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE [patent_app_type] => utility [patent_app_number] => 18/774379 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774379 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/774379
CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE Jul 15, 2024 Pending
Array ( [id] => 19561877 [patent_doc_number] => 20240373669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/773377 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773377 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773377
DISPLAY APPARATUS Jul 14, 2024 Pending
Array ( [id] => 20204181 [patent_doc_number] => 12406966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Device with embedded high-bandwidth, high-capacity memory using wafer bonding [patent_app_type] => utility [patent_app_number] => 18/767750 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 7717 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767750 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767750
Device with embedded high-bandwidth, high-capacity memory using wafer bonding Jul 8, 2024 Issued
Array ( [id] => 19531897 [patent_doc_number] => 20240355799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => DEEP PARTITION POWER DELIVERY WITH DEEP TRENCH CAPACITOR [patent_app_type] => utility [patent_app_number] => 18/762706 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762706 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/762706
DEEP PARTITION POWER DELIVERY WITH DEEP TRENCH CAPACITOR Jul 2, 2024 Pending
Array ( [id] => 19767388 [patent_doc_number] => 12225704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => 3D memory devices and structures with memory arrays and metal layers [patent_app_type] => utility [patent_app_number] => 18/731340 [patent_app_country] => US [patent_app_date] => 2024-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 148 [patent_no_of_words] => 41135 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731340 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/731340
3D memory devices and structures with memory arrays and metal layers Jun 1, 2024 Issued
Array ( [id] => 19468124 [patent_doc_number] => 20240321794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR CHIP HAVING A THROUGH ELECTRODE AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR CHIP [patent_app_type] => utility [patent_app_number] => 18/679806 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/679806
SEMICONDUCTOR CHIP HAVING A THROUGH ELECTRODE AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR CHIP May 30, 2024 Pending
Array ( [id] => 19486648 [patent_doc_number] => 20240334690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/676298 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676298 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676298
THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME May 27, 2024 Pending
Array ( [id] => 19486648 [patent_doc_number] => 20240334690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/676298 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676298 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676298
THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME May 27, 2024 Pending
Array ( [id] => 19437938 [patent_doc_number] => 20240306436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => PIXEL DEFINING LAYER, MANUFACTURING METHOD THEREFOR, AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 18/664180 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664180 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664180
PIXEL DEFINING LAYER, MANUFACTURING METHOD THEREFOR, AND DISPLAY PANEL May 13, 2024 Pending
Array ( [id] => 19436103 [patent_doc_number] => 20240304601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => Vertically Stacked Semiconductor Device Including a Hybrid Bond Contact Junction Circuit and Methods for Forming the Same [patent_app_type] => utility [patent_app_number] => 18/662749 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662749 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662749
Vertically Stacked Semiconductor Device Including a Hybrid Bond Contact Junction Circuit and Methods for Forming the Same May 12, 2024 Pending
Array ( [id] => 19436103 [patent_doc_number] => 20240304601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => Vertically Stacked Semiconductor Device Including a Hybrid Bond Contact Junction Circuit and Methods for Forming the Same [patent_app_type] => utility [patent_app_number] => 18/662749 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662749 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662749
Vertically Stacked Semiconductor Device Including a Hybrid Bond Contact Junction Circuit and Methods for Forming the Same May 12, 2024 Pending
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