Mamadou L. Diallo

Array ( [id] => 19223691 [patent_doc_number] => 20240188395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => DISPLAY PANEL AND DISPLAY TERMINAL [patent_app_type] => utility [patent_app_number] => 17/787516 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17787516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19223691 [patent_doc_number] => 20240188395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => DISPLAY PANEL AND DISPLAY TERMINAL [patent_app_type] => utility [patent_app_number] => 17/787516 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17787516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18797009 [patent_doc_number] => 11830844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/834923 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 42 [patent_no_of_words] => 17008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18983588 [patent_doc_number] => 11908777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor package with plurality of leads and sealing resin [patent_app_type] => utility [patent_app_number] => 17/826975 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 11718 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18983588 [patent_doc_number] => 11908777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor package with plurality of leads and sealing resin [patent_app_type] => utility [patent_app_number] => 17/826975 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 11718 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18983588 [patent_doc_number] => 11908777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor package with plurality of leads and sealing resin [patent_app_type] => utility [patent_app_number] => 17/826975 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 11718 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18983588 [patent_doc_number] => 11908777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor package with plurality of leads and sealing resin [patent_app_type] => utility [patent_app_number] => 17/826975 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 11718 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18250764 [patent_doc_number] => 20230077803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/751740 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18645663 [patent_doc_number] => 11769742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Semiconductor chip and semiconductor package including the same [patent_app_type] => utility [patent_app_number] => 17/747190 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 14816 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747190 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17840754 [patent_doc_number] => 20220278060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => MOLDED SEMICONDUCTOR PACKAGE WITH HIGH VOLTAGE ISOLATION [patent_app_type] => utility [patent_app_number] => 17/746306 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17949227 [patent_doc_number] => 20220336246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => METHOD FOR SUBSTRATE REGISTRATION AND ANCHORING IN INKJET PRINTING [patent_app_type] => utility [patent_app_number] => 17/735018 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18721546 [patent_doc_number] => 11798903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Methods of forming microvias with reduced diameter [patent_app_type] => utility [patent_app_number] => 17/725003 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5316 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18735670 [patent_doc_number] => 11804411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Secure inspection and marking of semiconductor wafers for trusted manufacturing thereof [patent_app_type] => utility [patent_app_number] => 17/718390 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8933 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18623852 [patent_doc_number] => 11756908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Package substrate including a redistribution pad extending from a redistribution layer and including segmenting grooves along a redial direction thereof and semiconductor package including the same [patent_app_type] => utility [patent_app_number] => 17/718639 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 6666 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18423982 [patent_doc_number] => 20230178446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => Highly Protective Wafer Edge Sidewall Protection Layer [patent_app_type] => utility [patent_app_number] => 17/657184 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17657184 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17723463 [patent_doc_number] => 20220216185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => BACKSIDE CONTACT TO IMPROVE THERMAL DISSIPATION AWAY FROM SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/703088 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19935304 [patent_doc_number] => 12308514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Thermal and electrical insulation structure [patent_app_type] => utility [patent_app_number] => 17/701340 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19918614 [patent_doc_number] => 12293990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Semiconductor integrated circuit comprising master chip with first buffer circuit and slave chiip with second buffer circuit [patent_app_type] => utility [patent_app_number] => 17/700965 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17700965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17708750 [patent_doc_number] => 20220208758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => METHODS FOR PILLAR CONNECTION ON FRONTSIDE AND PASSIVE DEVICE INTEGRATION ON BACKSIDE OF DIE [patent_app_type] => utility [patent_app_number] => 17/699680 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17708600 [patent_doc_number] => 20220208608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/655075 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17655075 [rel_patent_id] =>[rel_patent_doc_number] =>)