Search

Mamadou L. Diallo

Examiner (ID: 7519, Phone: (571)270-5449 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2895, 2897, 3648, 4174, 2819, 2811
Total Applications
1764
Issued Applications
1580
Pending Applications
90
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18221361 [patent_doc_number] => 20230060355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 17/462330 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462330 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462330
Semiconductor package structure and method for preparing the same Aug 30, 2021 Issued
Array ( [id] => 19213705 [patent_doc_number] => 12002777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Semiconductor device with bonded substrates [patent_app_type] => utility [patent_app_number] => 17/461550 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 6916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461550 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461550
Semiconductor device with bonded substrates Aug 29, 2021 Issued
Array ( [id] => 20390810 [patent_doc_number] => 12490560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Display panel and manufacturing method thereof, and display device [patent_app_type] => utility [patent_app_number] => 17/796091 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 4600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17796091 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/796091
Display panel and manufacturing method thereof, and display device Aug 26, 2021 Issued
Array ( [id] => 17277968 [patent_doc_number] => 20210384166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/408849 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408849 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408849
Chip package structure and manufacturing method thereof Aug 22, 2021 Issued
Array ( [id] => 18935505 [patent_doc_number] => 11887949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Bond pad layout including floating conductive sections [patent_app_type] => utility [patent_app_number] => 17/405812 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7356 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405812 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/405812
Bond pad layout including floating conductive sections Aug 17, 2021 Issued
Array ( [id] => 18207843 [patent_doc_number] => 20230054100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => CHIP AND SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/403925 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403925 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/403925
Chip having multiple functional units and semiconductor structure using the same Aug 16, 2021 Issued
Array ( [id] => 18373327 [patent_doc_number] => 11653519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Display device and electronic apparatus with contact electrode electrically connected to cathode electrode at concave area locations [patent_app_type] => utility [patent_app_number] => 17/399787 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 11206 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399787
Display device and electronic apparatus with contact electrode electrically connected to cathode electrode at concave area locations Aug 10, 2021 Issued
Array ( [id] => 18144363 [patent_doc_number] => 20230018214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => Semiconductor bonding structure [patent_app_type] => utility [patent_app_number] => 17/398017 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398017 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398017
Semiconductor bonding structure Aug 9, 2021 Issued
Array ( [id] => 18277070 [patent_doc_number] => 11616018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Semiconductor devices including a thick metal layer [patent_app_type] => utility [patent_app_number] => 17/398043 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 10224 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398043 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398043
Semiconductor devices including a thick metal layer Aug 9, 2021 Issued
Array ( [id] => 17247170 [patent_doc_number] => 20210366915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => 4CPP SRAM CELL AND ARRAY [patent_app_type] => utility [patent_app_number] => 17/397371 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397371
4CPP SRAM cell and array Aug 8, 2021 Issued
Array ( [id] => 17247173 [patent_doc_number] => 20210366918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => ONE-TIME PROGRAMMABLE MEMORY DEVICE INCLUDING ANTI-FUSE ELEMENT AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/393621 [patent_app_country] => US [patent_app_date] => 2021-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393621 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393621
One-time programmable memory device including anti-fuse element and manufacturing method thereof Aug 3, 2021 Issued
Array ( [id] => 18235989 [patent_doc_number] => 11600553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Semiconductor device including through substrate vias and method of manufacturing the semiconductor device [patent_app_type] => utility [patent_app_number] => 17/381287 [patent_app_country] => US [patent_app_date] => 2021-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 13472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381287 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/381287
Semiconductor device including through substrate vias and method of manufacturing the semiconductor device Jul 20, 2021 Issued
Array ( [id] => 18068207 [patent_doc_number] => 20220399295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => SEMICONDUCTOR STRUCTURE FOR WAFER LEVEL BONDING AND BONDED SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/382325 [patent_app_country] => US [patent_app_date] => 2021-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/382325
Semiconductor structure for wafer level bonding and bonded semiconductor structure Jul 20, 2021 Issued
Array ( [id] => 18767008 [patent_doc_number] => 11817420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Systems and methods for direct bonding in semiconductor die manufacturing [patent_app_type] => utility [patent_app_number] => 17/379568 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6699 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379568 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379568
Systems and methods for direct bonding in semiconductor die manufacturing Jul 18, 2021 Issued
Array ( [id] => 18935522 [patent_doc_number] => 11887966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Semiconductor packages [patent_app_type] => utility [patent_app_number] => 17/376784 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 11094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376784 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/376784
Semiconductor packages Jul 14, 2021 Issued
Array ( [id] => 18357992 [patent_doc_number] => 11646399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Display device including display modules and light absorbing pattern for covering gap between display modules and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/375780 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375780 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/375780
Display device including display modules and light absorbing pattern for covering gap between display modules and method for manufacturing the same Jul 13, 2021 Issued
Array ( [id] => 18735785 [patent_doc_number] => 11804527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Transistor with center fed gate [patent_app_type] => utility [patent_app_number] => 17/376026 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7247 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/376026
Transistor with center fed gate Jul 13, 2021 Issued
Array ( [id] => 18528751 [patent_doc_number] => 11715756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Device structure and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/368343 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17368343 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/368343
Device structure and methods of forming the same Jul 5, 2021 Issued
Array ( [id] => 17566662 [patent_doc_number] => 20220130811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => STACKED-CHIP PACKAGES [patent_app_type] => utility [patent_app_number] => 17/368028 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17368028 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/368028
Stacked-chip packages having through vias Jul 5, 2021 Issued
Array ( [id] => 18857448 [patent_doc_number] => 11855044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Semiconductor package utilizing a hybrid bonding process and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/367005 [patent_app_country] => US [patent_app_date] => 2021-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 9484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17367005 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/367005
Semiconductor package utilizing a hybrid bonding process and method of manufacturing the same Jul 1, 2021 Issued
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