Search

Mamadou L. Diallo

Examiner (ID: 7519, Phone: (571)270-5449 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2895, 2897, 3648, 4174, 2819, 2811
Total Applications
1764
Issued Applications
1580
Pending Applications
90
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19804114 [patent_doc_number] => 20250070039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/632486 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632486 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/632486
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Apr 10, 2024 Pending
Array ( [id] => 20292921 [patent_doc_number] => 20250318164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => Insulated Gate Bipolar Transistor Having Improved Electrical Performance [patent_app_type] => utility [patent_app_number] => 18/628735 [patent_app_country] => US [patent_app_date] => 2024-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18628735 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/628735
Insulated Gate Bipolar Transistor Having Improved Electrical Performance Apr 6, 2024 Pending
Array ( [id] => 19308880 [patent_doc_number] => 20240237463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => DISPLAY SUBSTRATE AND RELATED DEVICES [patent_app_type] => utility [patent_app_number] => 18/617013 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 411 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18617013 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/617013
Display substrate and related devices with improved resolution Mar 25, 2024 Issued
Array ( [id] => 19305675 [patent_doc_number] => 20240234255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => SEMICONDUCTOR CHIP INCLUDING THROUGH ELECTRODE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/615528 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615528 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615528
Semiconductor chip including through electrode, and semiconductor package including the same Mar 24, 2024 Issued
Array ( [id] => 20346074 [patent_doc_number] => 12469809 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Semiconductor interconnect structures with vertically offset bonding surfaces, and associated systems and methods [patent_app_type] => utility [patent_app_number] => 18/610263 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 5604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610263 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610263
Semiconductor interconnect structures with vertically offset bonding surfaces, and associated systems and methods Mar 19, 2024 Issued
Array ( [id] => 19384639 [patent_doc_number] => 20240274509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING THROUGH-ELECTRODES [patent_app_type] => utility [patent_app_number] => 18/610651 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610651 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610651
SEMICONDUCTOR DEVICE INCLUDING THROUGH-ELECTRODES Mar 19, 2024 Pending
Array ( [id] => 20080904 [patent_doc_number] => 12354982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Memory devices with backside bond pads under a memory array [patent_app_type] => utility [patent_app_number] => 18/607339 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607339 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607339
Memory devices with backside bond pads under a memory array Mar 14, 2024 Issued
Array ( [id] => 19285855 [patent_doc_number] => 20240222332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => BONDED WAFER DEVICE STRUCTURE AND METHODS FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 18/604542 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604542 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604542
Bonded wafer device structure and methods for making the same Mar 13, 2024 Issued
Array ( [id] => 20230433 [patent_doc_number] => 12419098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Device integration schemes leveraging a bulk semiconductor substrate having a <111> crystal orientation [patent_app_type] => utility [patent_app_number] => 18/604627 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604627 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604627
Device integration schemes leveraging a bulk semiconductor substrate having a <111> crystal orientation Mar 13, 2024 Issued
Array ( [id] => 20036375 [patent_doc_number] => 20250174597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => EMBEDDED INTEGRATED VOLTAGE REGULATOR [patent_app_type] => utility [patent_app_number] => 18/603073 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603073 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/603073
EMBEDDED INTEGRATED VOLTAGE REGULATOR Mar 11, 2024 Pending
Array ( [id] => 21014508 [patent_doc_number] => 12751006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-29 [patent_title] => Integrated circuit device and electronic system including the same [patent_app_type] => utility [patent_app_number] => 18/602778 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602778 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602778
INTEGRATED CIRCUIT DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME Mar 11, 2024 Pending
Array ( [id] => 20996740 [patent_doc_number] => 12745398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-22 [patent_title] => Semiconductor memory device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/602979 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 33 [patent_no_of_words] => 5937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602979 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602979
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME Mar 11, 2024 Pending
Array ( [id] => 20235514 [patent_doc_number] => 20250292833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => MEMORY DEVICE CONTAINING NON-INTEGER AVERAGE NUMBER OF MEMORY OPENING FILL STRUCTURES PER COLUMN [patent_app_type] => utility [patent_app_number] => 18/602790 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602790 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602790
MEMORY DEVICE CONTAINING NON-INTEGER AVERAGE NUMBER OF MEMORY OPENING FILL STRUCTURES PER COLUMN Mar 11, 2024 Pending
Array ( [id] => 19269489 [patent_doc_number] => 20240213193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => DEVICE FOR CONTROLLING TRAPPED IONS [patent_app_type] => utility [patent_app_number] => 18/594703 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594703 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594703
Device for controlling trapped ions Mar 3, 2024 Issued
Array ( [id] => 19321634 [patent_doc_number] => 20240243181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => Trench Gate Semiconductor Device, and Manufacturing Method Thereof [patent_app_type] => utility [patent_app_number] => 18/581921 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581921 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581921
Trench Gate Semiconductor Device, and Manufacturing Method Thereof Feb 19, 2024 Pending
Array ( [id] => 20245923 [patent_doc_number] => 12426268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Semiconductor memory having memory cell regions and other regions alternately along a bit line direction [patent_app_type] => utility [patent_app_number] => 18/440623 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440623 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440623
Semiconductor memory having memory cell regions and other regions alternately along a bit line direction Feb 12, 2024 Issued
Array ( [id] => 19206455 [patent_doc_number] => 20240178354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => METASURFACE FOR IMPROVING A LIGHT EXTRACTION EFFICIENCY OF A LIGHT-EMITTING DIODE [patent_app_type] => utility [patent_app_number] => 18/432070 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432070 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/432070
METASURFACE FOR IMPROVING A LIGHT EXTRACTION EFFICIENCY OF A LIGHT-EMITTING DIODE Feb 4, 2024 Pending
Array ( [id] => 19315955 [patent_doc_number] => 12041791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => 3D memory devices and structures with memory arrays and metal layers [patent_app_type] => utility [patent_app_number] => 18/431177 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 147 [patent_no_of_words] => 40673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431177 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/431177
3D memory devices and structures with memory arrays and metal layers Feb 1, 2024 Issued
Array ( [id] => 19206272 [patent_doc_number] => 20240178171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SEMICONDUCTOR STRUCTURE FOR WAFER LEVEL BONDING AND BONDED SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/429477 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429477 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429477
Semiconductor structure for wafer level bonding and bonded semiconductor structure Jan 31, 2024 Issued
Array ( [id] => 20138492 [patent_doc_number] => 20250245536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => RESONATOR QUBIT SYSTEM [patent_app_type] => utility [patent_app_number] => 18/427131 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427131 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/427131
RESONATOR QUBIT SYSTEM Jan 29, 2024 Pending
Menu