Search

Mamadou L. Diallo

Examiner (ID: 18306)

Most Active Art Unit
2895
Art Unit(s)
3648, 2897, 2819, 2895, 2811, 4174
Total Applications
1724
Issued Applications
1539
Pending Applications
108
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19392862 [patent_doc_number] => 20240282732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => SEMICONDUCTOR PACKAGES WITH STACKED DIES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/650225 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17281 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650225 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/650225
SEMICONDUCTOR PACKAGES WITH STACKED DIES AND METHODS OF FORMING THE SAME Apr 29, 2024 Pending
Array ( [id] => 19517787 [patent_doc_number] => 20240349473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => 4CPP SRAM CELL AND ARRAY [patent_app_type] => utility [patent_app_number] => 18/643753 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643753 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643753
4CPP SRAM CELL AND ARRAY Apr 22, 2024 Pending
Array ( [id] => 19308880 [patent_doc_number] => 20240237463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => DISPLAY SUBSTRATE AND RELATED DEVICES [patent_app_type] => utility [patent_app_number] => 18/617013 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 411 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18617013 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/617013
Display substrate and related devices with improved resolution Mar 25, 2024 Issued
Array ( [id] => 19305675 [patent_doc_number] => 20240234255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => SEMICONDUCTOR CHIP INCLUDING THROUGH ELECTRODE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/615528 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615528 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615528
Semiconductor chip including through electrode, and semiconductor package including the same Mar 24, 2024 Issued
Array ( [id] => 20346074 [patent_doc_number] => 12469809 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Semiconductor interconnect structures with vertically offset bonding surfaces, and associated systems and methods [patent_app_type] => utility [patent_app_number] => 18/610263 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 5604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610263 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610263
Semiconductor interconnect structures with vertically offset bonding surfaces, and associated systems and methods Mar 19, 2024 Issued
Array ( [id] => 20080904 [patent_doc_number] => 12354982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Memory devices with backside bond pads under a memory array [patent_app_type] => utility [patent_app_number] => 18/607339 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607339 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607339
Memory devices with backside bond pads under a memory array Mar 14, 2024 Issued
Array ( [id] => 20230433 [patent_doc_number] => 12419098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Device integration schemes leveraging a bulk semiconductor substrate having a <111> crystal orientation [patent_app_type] => utility [patent_app_number] => 18/604627 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604627 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604627
Device integration schemes leveraging a bulk semiconductor substrate having a <111> crystal orientation Mar 13, 2024 Issued
Array ( [id] => 19285855 [patent_doc_number] => 20240222332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => BONDED WAFER DEVICE STRUCTURE AND METHODS FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 18/604542 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604542 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604542
Bonded wafer device structure and methods for making the same Mar 13, 2024 Issued
Array ( [id] => 19269489 [patent_doc_number] => 20240213193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => DEVICE FOR CONTROLLING TRAPPED IONS [patent_app_type] => utility [patent_app_number] => 18/594703 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594703 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594703
Device for controlling trapped ions Mar 3, 2024 Issued
Array ( [id] => 20245923 [patent_doc_number] => 12426268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Semiconductor memory having memory cell regions and other regions alternately along a bit line direction [patent_app_type] => utility [patent_app_number] => 18/440623 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440623 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440623
Semiconductor memory having memory cell regions and other regions alternately along a bit line direction Feb 12, 2024 Issued
Array ( [id] => 19315955 [patent_doc_number] => 12041791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => 3D memory devices and structures with memory arrays and metal layers [patent_app_type] => utility [patent_app_number] => 18/431177 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 147 [patent_no_of_words] => 40673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431177 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/431177
3D memory devices and structures with memory arrays and metal layers Feb 1, 2024 Issued
Array ( [id] => 19206272 [patent_doc_number] => 20240178171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SEMICONDUCTOR STRUCTURE FOR WAFER LEVEL BONDING AND BONDED SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/429477 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429477 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429477
Semiconductor structure for wafer level bonding and bonded semiconductor structure Jan 31, 2024 Issued
Array ( [id] => 19206272 [patent_doc_number] => 20240178171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SEMICONDUCTOR STRUCTURE FOR WAFER LEVEL BONDING AND BONDED SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/429477 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429477 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429477
Semiconductor structure for wafer level bonding and bonded semiconductor structure Jan 31, 2024 Issued
Array ( [id] => 19206272 [patent_doc_number] => 20240178171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SEMICONDUCTOR STRUCTURE FOR WAFER LEVEL BONDING AND BONDED SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/429477 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429477 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429477
Semiconductor structure for wafer level bonding and bonded semiconductor structure Jan 31, 2024 Issued
Array ( [id] => 19252972 [patent_doc_number] => 20240203969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => STACKED-CHIP PACKAGES [patent_app_type] => utility [patent_app_number] => 18/418964 [patent_app_country] => US [patent_app_date] => 2024-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418964 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/418964
Stacked-chip packages Jan 21, 2024 Issued
Array ( [id] => 19146365 [patent_doc_number] => 20240145395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => INTERCONNECT ARCHITECTURE WITH SILICON INTERPOSER AND EMIB [patent_app_type] => utility [patent_app_number] => 18/406018 [patent_app_country] => US [patent_app_date] => 2024-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406018 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406018
Interconnect architecture with silicon interposer and EMIB Jan 4, 2024 Issued
Array ( [id] => 19146365 [patent_doc_number] => 20240145395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => INTERCONNECT ARCHITECTURE WITH SILICON INTERPOSER AND EMIB [patent_app_type] => utility [patent_app_number] => 18/406018 [patent_app_country] => US [patent_app_date] => 2024-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406018 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406018
Interconnect architecture with silicon interposer and EMIB Jan 4, 2024 Issued
Array ( [id] => 19305794 [patent_doc_number] => 20240234374 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/400497 [patent_app_country] => US [patent_app_date] => 2023-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400497 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/400497
Semiconductor package Dec 28, 2023 Issued
Array ( [id] => 19305794 [patent_doc_number] => 20240234374 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/400497 [patent_app_country] => US [patent_app_date] => 2023-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400497 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/400497
Semiconductor package Dec 28, 2023 Issued
Array ( [id] => 19101139 [patent_doc_number] => 20240120367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => STANDALONE ISOLATION CAPACITOR [patent_app_type] => utility [patent_app_number] => 18/390395 [patent_app_country] => US [patent_app_date] => 2023-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18390395 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/390395
Standalone isolation capacitor Dec 19, 2023 Issued
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