Search

Mamadou L. Diallo

Examiner (ID: 18306)

Most Active Art Unit
2895
Art Unit(s)
3648, 2897, 2819, 2895, 2811, 4174
Total Applications
1724
Issued Applications
1539
Pending Applications
108
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19531787 [patent_doc_number] => 20240355689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => STACKED LAYERS WITH FILLING STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/348170 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348170 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348170
STACKED LAYERS WITH FILLING STRUCTURES Jul 5, 2023 Pending
Array ( [id] => 18729441 [patent_doc_number] => 20230343737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/346550 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346550 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346550
Semiconductor packages and methods of forming the same Jul 2, 2023 Issued
Array ( [id] => 19654503 [patent_doc_number] => 12176303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Wafer-level bonding of obstructive elements [patent_app_type] => utility [patent_app_number] => 18/346396 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 34 [patent_no_of_words] => 9344 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346396 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346396
Wafer-level bonding of obstructive elements Jul 2, 2023 Issued
Array ( [id] => 18898789 [patent_doc_number] => 20240014274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => BIDIRECTIONAL SWITCHING DEVICES, ITS TERMINAL STRUCTURES, AND ELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 18/213952 [patent_app_country] => US [patent_app_date] => 2023-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6491 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18213952 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/213952
BIDIRECTIONAL SWITCHING DEVICES, ITS TERMINAL STRUCTURES, AND ELECTRONIC DEVICES Jun 25, 2023 Pending
Array ( [id] => 18898789 [patent_doc_number] => 20240014274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => BIDIRECTIONAL SWITCHING DEVICES, ITS TERMINAL STRUCTURES, AND ELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 18/213952 [patent_app_country] => US [patent_app_date] => 2023-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6491 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18213952 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/213952
BIDIRECTIONAL SWITCHING DEVICES, ITS TERMINAL STRUCTURES, AND ELECTRONIC DEVICES Jun 25, 2023 Pending
Array ( [id] => 18712945 [patent_doc_number] => 20230335578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => DEVICE STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/211561 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211561 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/211561
Device structure with a redistribution layer and a buffer layer Jun 18, 2023 Issued
Array ( [id] => 19627178 [patent_doc_number] => 12166027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Copper-bonded memory stacks with copper-bonded interconnection memory systems [patent_app_type] => utility [patent_app_number] => 18/335578 [patent_app_country] => US [patent_app_date] => 2023-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5057 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18335578 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/335578
Copper-bonded memory stacks with copper-bonded interconnection memory systems Jun 14, 2023 Issued
Array ( [id] => 19634650 [patent_doc_number] => 20240413099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => MULTI-DIE PHYSICALLY UNCLONABLE FUNCTION ENTROPY SOURCE [patent_app_type] => utility [patent_app_number] => 18/207378 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18207378 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/207378
MULTI-DIE PHYSICALLY UNCLONABLE FUNCTION ENTROPY SOURCE Jun 7, 2023 Pending
Array ( [id] => 18761566 [patent_doc_number] => 11812620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => 3D DRAM memory devices and structures with control circuits [patent_app_type] => utility [patent_app_number] => 18/206040 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 148 [patent_no_of_words] => 39203 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206040 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206040
3D DRAM memory devices and structures with control circuits Jun 4, 2023 Issued
Array ( [id] => 18821206 [patent_doc_number] => 20230395547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/205329 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18205329 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/205329
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Jun 1, 2023 Pending
Array ( [id] => 19305783 [patent_doc_number] => 20240234363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => BONDING LAYER AND PROCESS [patent_app_type] => utility [patent_app_number] => 18/320791 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320791 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/320791
BONDING LAYER AND PROCESS May 18, 2023 Pending
Array ( [id] => 19305783 [patent_doc_number] => 20240234363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => BONDING LAYER AND PROCESS [patent_app_type] => utility [patent_app_number] => 18/320791 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320791 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/320791
BONDING LAYER AND PROCESS May 18, 2023 Pending
Array ( [id] => 18633629 [patent_doc_number] => 20230292556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/198163 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18198163 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/198163
Display apparatus that includes concavo-convex structure on upper surface of pixel defining layer and method of manufacturing the same May 15, 2023 Issued
Array ( [id] => 20332903 [patent_doc_number] => 12463188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Flip-chip packaged power transistor module having built-in gate driver [patent_app_type] => utility [patent_app_number] => 18/197607 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197607 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/197607
Flip-chip packaged power transistor module having built-in gate driver May 14, 2023 Issued
Array ( [id] => 20332903 [patent_doc_number] => 12463188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Flip-chip packaged power transistor module having built-in gate driver [patent_app_type] => utility [patent_app_number] => 18/197607 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197607 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/197607
Flip-chip packaged power transistor module having built-in gate driver May 14, 2023 Issued
Array ( [id] => 19575446 [patent_doc_number] => 20240379738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => STRUCTURE AND FORMATION METHOD OF INTEGRATED CHIPS PACKAGE WITH CAPACITOR [patent_app_type] => utility [patent_app_number] => 18/314939 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314939 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314939
STRUCTURE AND FORMATION METHOD OF INTEGRATED CHIPS PACKAGE WITH CAPACITOR May 9, 2023 Pending
Array ( [id] => 18600269 [patent_doc_number] => 20230275070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/195096 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18195096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/195096
Chip package structure and manufacturing method thereof May 8, 2023 Issued
Array ( [id] => 18601855 [patent_doc_number] => 20230276661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/144744 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18144744 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/144744
DISPLAY DEVICE May 7, 2023 Pending
Array ( [id] => 19560017 [patent_doc_number] => 20240371809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => STRUCTURE INCLUDING PASSIVE COMPONENT TRAVERSING MULTIPLE SEMICONDUCTOR CHIPS, WITH RELATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/311712 [patent_app_country] => US [patent_app_date] => 2023-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311712 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/311712
STRUCTURE INCLUDING PASSIVE COMPONENT TRAVERSING MULTIPLE SEMICONDUCTOR CHIPS, WITH RELATED METHODS AND SYSTEMS May 2, 2023 Pending
Array ( [id] => 19546528 [patent_doc_number] => 20240363564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SEMICONDUCTOR DEVICES WITH HYBRID BONDING LAYERS AND PROCESS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 18/309678 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309678 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/309678
SEMICONDUCTOR DEVICES WITH HYBRID BONDING LAYERS AND PROCESS OF MAKING THE SAME Apr 27, 2023 Pending
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