Search

Mamadou L. Diallo

Examiner (ID: 18306)

Most Active Art Unit
2895
Art Unit(s)
3648, 2897, 2819, 2895, 2811, 4174
Total Applications
1724
Issued Applications
1539
Pending Applications
108
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18324403 [patent_doc_number] => 20230122531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => REDUCED PARASITIC CAPACITANCE IN BONDED STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/046717 [patent_app_country] => US [patent_app_date] => 2022-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18046717 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/046717
REDUCED PARASITIC CAPACITANCE IN BONDED STRUCTURES Oct 13, 2022 Pending
Array ( [id] => 18198291 [patent_doc_number] => 20230051810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => CHEMICAL BONDING METHOD, PACKAGE-TYPE ELECTRONIC COMPONENT, AND HYBRID BONDING METHOD FOR ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/962061 [patent_app_country] => US [patent_app_date] => 2022-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -38 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17962061 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/962061
Chemical bonding method, package-type electronic component, and hybrid bonding method for electronic device Oct 6, 2022 Issued
Array ( [id] => 19086204 [patent_doc_number] => 20240113005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => HYBRID BONDING TECHNOLOGIES WITH THERMAL EXPANSION COMPENSATION STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/957751 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17957751 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/957751
Hybrid bonding technologies with thermal expansion compensation structures Sep 29, 2022 Issued
Array ( [id] => 18394868 [patent_doc_number] => 20230163089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 17/934298 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934298 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/934298
SEMICONDUCTOR PACKAGES Sep 21, 2022 Pending
Array ( [id] => 18284560 [patent_doc_number] => 20230100032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => BONDED STRUCTURE WITH ACTIVE INTERPOSER [patent_app_type] => utility [patent_app_number] => 17/934514 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934514 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/934514
BONDED STRUCTURE WITH ACTIVE INTERPOSER Sep 21, 2022 Pending
Array ( [id] => 19054814 [patent_doc_number] => 20240096783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => FLEXIBLE WIRING ARCHITECTURE FOR MULTI-DIE INTEGRATION [patent_app_type] => utility [patent_app_number] => 17/948664 [patent_app_country] => US [patent_app_date] => 2022-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17948664 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/948664
FLEXIBLE WIRING ARCHITECTURE FOR MULTI-DIE INTEGRATION Sep 19, 2022 Pending
Array ( [id] => 18141145 [patent_doc_number] => 20230014987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/946326 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946326 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/946326
Semiconductor package Sep 15, 2022 Issued
Array ( [id] => 20118401 [patent_doc_number] => 12368119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/944430 [patent_app_country] => US [patent_app_date] => 2022-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17944430 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/944430
Semiconductor package Sep 13, 2022 Issued
Array ( [id] => 20118401 [patent_doc_number] => 12368119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/944430 [patent_app_country] => US [patent_app_date] => 2022-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17944430 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/944430
Semiconductor package Sep 13, 2022 Issued
Array ( [id] => 19007914 [patent_doc_number] => 20240071985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => PARTITIONING WAFER PROCESSING AND HYBRID BONDING OF LAYERS FORMED ON DIFFERENT WAFERS FOR A SEMICONDUCTOR ASSEMBLY [patent_app_type] => utility [patent_app_number] => 17/896746 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896746 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/896746
PARTITIONING WAFER PROCESSING AND HYBRID BONDING OF LAYERS FORMED ON DIFFERENT WAFERS FOR A SEMICONDUCTOR ASSEMBLY Aug 25, 2022 Pending
Array ( [id] => 19007914 [patent_doc_number] => 20240071985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => PARTITIONING WAFER PROCESSING AND HYBRID BONDING OF LAYERS FORMED ON DIFFERENT WAFERS FOR A SEMICONDUCTOR ASSEMBLY [patent_app_type] => utility [patent_app_number] => 17/896746 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896746 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/896746
PARTITIONING WAFER PROCESSING AND HYBRID BONDING OF LAYERS FORMED ON DIFFERENT WAFERS FOR A SEMICONDUCTOR ASSEMBLY Aug 25, 2022 Pending
Array ( [id] => 19007957 [patent_doc_number] => 20240072028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => BONDED ASSEMBLY CONTAINING CONDUCTIVE VIA STRUCTURES EXTENDING THROUGH WORD LINES IN A STAIRCASE REGION AND METHODS FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/822182 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17822182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/822182
Bonded assembly containing conductive via structures extending through word lines in a staircase region and methods for making the same Aug 24, 2022 Issued
Array ( [id] => 18661373 [patent_doc_number] => 20230307387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/822248 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17822248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/822248
Memory device Aug 24, 2022 Issued
Array ( [id] => 19007930 [patent_doc_number] => 20240072001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => SEPARATED INPUT/OUTPUT (I/O) AND SHARED POWER TERMINALS FOR A CARRIER WAFER WITH A BUILT-IN DEVICE FOR BONDING WITH ANOTHER DEVICE WAFER [patent_app_type] => utility [patent_app_number] => 17/821808 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17821808 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/821808
SEPARATED INPUT/OUTPUT (I/O) AND SHARED POWER TERMINALS FOR A CARRIER WAFER WITH A BUILT-IN DEVICE FOR BONDING WITH ANOTHER DEVICE WAFER Aug 23, 2022 Pending
Array ( [id] => 18789464 [patent_doc_number] => 20230378134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => STACKED INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/893806 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -51 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893806 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893806
STACKED INTEGRATED CIRCUIT Aug 22, 2022 Pending
Array ( [id] => 18789464 [patent_doc_number] => 20230378134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => STACKED INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/893806 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -51 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893806 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893806
STACKED INTEGRATED CIRCUIT Aug 22, 2022 Pending
Array ( [id] => 19007397 [patent_doc_number] => 20240071468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => WORD LINE DRIVERS FOR MULTIPLE-DIE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/893672 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893672 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893672
Word line drivers for multiple-die memory devices Aug 22, 2022 Issued
Array ( [id] => 18991183 [patent_doc_number] => 20240063152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => HYBRID BONDING FOR SEMICONDUCTOR DEVICE ASSEMBLIES [patent_app_type] => utility [patent_app_number] => 17/893160 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893160 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893160
HYBRID BONDING FOR SEMICONDUCTOR DEVICE ASSEMBLIES Aug 21, 2022 Pending
Array ( [id] => 20346073 [patent_doc_number] => 12469808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Semiconductor package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/892102 [patent_app_country] => US [patent_app_date] => 2022-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 1969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/892102
Semiconductor package and manufacturing method thereof Aug 20, 2022 Issued
Array ( [id] => 18991163 [patent_doc_number] => 20240063132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => PACKAGE ARCHITECTURE OF LARGE DIES USING QUASI-MONOLITHIC CHIP LAYERS [patent_app_type] => utility [patent_app_number] => 17/820993 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17820993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/820993
PACKAGE ARCHITECTURE OF LARGE DIES USING QUASI-MONOLITHIC CHIP LAYERS Aug 18, 2022 Pending
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