
Mamadou L. Diallo
Examiner (ID: 7519, Phone: (571)270-5449 , Office: P/2895 )
| Most Active Art Unit | 2895 |
| Art Unit(s) | 2895, 2897, 3648, 4174, 2819, 2811 |
| Total Applications | 1764 |
| Issued Applications | 1580 |
| Pending Applications | 90 |
| Abandoned Applications | 112 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
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