Mamon A. Obeid

Array ( [id] => 19269029 [patent_doc_number] => 20240212733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => METHODS AND CIRCUITS FOR READING AND WRITING PI-STATE-INDUCED CIRCULATING CURRENTS INTO SUPERCONDUCTING CIRCUITS CONTAINING MAGNETIC JOSEPHSON JUNCTIONS [patent_app_type] => utility [patent_app_number] => 18/478140 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18478140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19531503 [patent_doc_number] => 20240355405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => APPRATUS AND METHOD FOR CHANGING A READ VOLTAGE APPLIED FOR READING DATA FROM A NON-VOLATILE MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/469562 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19765723 [patent_doc_number] => 12224021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Memory device with leakage current verifying circuit for minimizing leakage current [patent_app_type] => utility [patent_app_number] => 18/469567 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5342 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 529 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19850387 [patent_doc_number] => 20250095738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => THRESHOLD VOLTAGE BUDGET BY EMPLOYING AN OXIDE-NITRIDE PITCH DEPENDENT THRESHOLD VOLTAGE WINDOW [patent_app_type] => utility [patent_app_number] => 18/369028 [patent_app_country] => US [patent_app_date] => 2023-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18369028 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20132081 [patent_doc_number] => 12374398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Forming operation of resistive memory device [patent_app_type] => utility [patent_app_number] => 18/457377 [patent_app_country] => US [patent_app_date] => 2023-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18457377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19531475 [patent_doc_number] => 20240355377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => MEMORY DEVICE FOR SELF-SEARCHING FOR BOUNDARY WORD LINE, METHOD FOR OPERATING MEMORY DEVICE, AND MEMORY SYSTEM INCLUDING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/455625 [patent_app_country] => US [patent_app_date] => 2023-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18820837 [patent_doc_number] => 20230395178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => CONTROLLING MEMORY INCLUDING MANAGING A CORRECTION VALUE TABLE [patent_app_type] => utility [patent_app_number] => 18/453567 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18820797 [patent_doc_number] => 20230395138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => Systems and Methods for Reducing Standby Power in Floating Body Memory Devices [patent_app_type] => utility [patent_app_number] => 18/235478 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18235478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20203963 [patent_doc_number] => 12406746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Semiconductor storage apparatus capable of efficiently performing screening test [patent_app_type] => utility [patent_app_number] => 18/451113 [patent_app_country] => US [patent_app_date] => 2023-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 1193 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19285342 [patent_doc_number] => 20240221819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => MEMORY DEVICES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/234333 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18234333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19687699 [patent_doc_number] => 20250006244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => ASYMMETRIC PASS VOLTAGE SCHEME FOR NON-VOLATILE MEMORY APPARATUS SIZE REDUCTION [patent_app_type] => utility [patent_app_number] => 18/233640 [patent_app_country] => US [patent_app_date] => 2023-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18233640 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19773110 [patent_doc_number] => 20250054536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/448479 [patent_app_country] => US [patent_app_date] => 2023-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19191173 [patent_doc_number] => 20240170086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => METHOD FOR OPERATING A MEMORY DEVICE AND MEMORY DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 18/360530 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19269078 [patent_doc_number] => 20240212782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY CONTROLLER, AN OPERATION METHOD THEREOF, A MEMORY DEVICE, AND A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/226340 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19452408 [patent_doc_number] => 20240312538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => NON-VOLATILE MEMORY WITH INTELLIGENT ERASE TESTING TO AVOID NEIGHBOR PLANE DISTURB [patent_app_type] => utility [patent_app_number] => 18/358651 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18865625 [patent_doc_number] => 20230420062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/357883 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19221239 [patent_doc_number] => 20240185943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => BINARY SEARCH BIT ERROR RATE ESTIMATION SCAN FOR NON-VOLATILE MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/219387 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18219387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20118217 [patent_doc_number] => 12367932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Memory device in which latch is coupled to source line and method of operation [patent_app_type] => utility [patent_app_number] => 18/218415 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 3514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20482651 [patent_doc_number] => 12531127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Compact CAM array for decision tree inference (tree-CAM) [patent_app_type] => utility [patent_app_number] => 18/347318 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19363941 [patent_doc_number] => 20240265975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => NAND FLASH MEMORY DEVICE WITH ENHANCED DATA RETENTION CHARACTERISTICS AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/340473 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340473 [rel_patent_id] =>[rel_patent_doc_number] =>)