
Mamon A. Obeid
Examiner (ID: 9872, Phone: (571)270-1813 , Office: P/3685 )
| Most Active Art Unit | 3685 |
| Art Unit(s) | 3621, 3699, 3686, 3685, 3687 |
| Total Applications | 465 |
| Issued Applications | 208 |
| Pending Applications | 14 |
| Abandoned Applications | 247 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18652794
[patent_doc_number] => 20230298634
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-21
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/897710
[patent_app_country] => US
[patent_app_date] => 2022-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14632
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897710
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/897710 | Semiconductor memory device and method for manufacturing semiconductor memory device | Aug 28, 2022 | Issued |
Array
(
[id] => 19007405
[patent_doc_number] => 20240071476
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-29
[patent_title] => STREAMING MODE FOR ACCESSING MEMORY CELLS IN A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/898346
[patent_app_country] => US
[patent_app_date] => 2022-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16901
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -26
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898346
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/898346 | STREAMING MODE FOR ACCESSING MEMORY CELLS IN A MEMORY DEVICE | Aug 28, 2022 | Pending |
Array
(
[id] => 19670631
[patent_doc_number] => 12183398
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-31
[patent_title] => Memory system with semiconductor storage device and memory controller for performing read verification
[patent_app_type] => utility
[patent_app_number] => 17/897695
[patent_app_country] => US
[patent_app_date] => 2022-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 16
[patent_no_of_words] => 12275
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897695
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/897695 | Memory system with semiconductor storage device and memory controller for performing read verification | Aug 28, 2022 | Issued |
Array
(
[id] => 18097049
[patent_doc_number] => 20220415390
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-29
[patent_title] => HIGH VOLTAGE SWITCH WITH MITIGATED GATE STRESS
[patent_app_type] => utility
[patent_app_number] => 17/896854
[patent_app_country] => US
[patent_app_date] => 2022-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18351
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896854
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/896854 | High voltage switch with mitigated gate stress | Aug 25, 2022 | Issued |
Array
(
[id] => 18224082
[patent_doc_number] => 20230063076
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => CONTENT ADDRESSABLE MEMORY DEVICE AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/893646
[patent_app_country] => US
[patent_app_date] => 2022-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14161
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893646
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/893646 | Content addressable memory device and operating method thereof | Aug 22, 2022 | Issued |
Array
(
[id] => 18067356
[patent_doc_number] => 20220398444
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-15
[patent_title] => Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network
[patent_app_type] => utility
[patent_app_number] => 17/893071
[patent_app_country] => US
[patent_app_date] => 2022-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15576
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893071
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/893071 | Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network | Aug 21, 2022 | Pending |
Array
(
[id] => 18079952
[patent_doc_number] => 20220405564
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-22
[patent_title] => Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network
[patent_app_type] => utility
[patent_app_number] => 17/893075
[patent_app_country] => US
[patent_app_date] => 2022-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15581
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893075
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/893075 | Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network | Aug 21, 2022 | Pending |
Array
(
[id] => 18061475
[patent_doc_number] => 20220392561
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-08
[patent_title] => OPTIMIZED STORAGE CHARGE LOSS MANAGEMENT
[patent_app_type] => utility
[patent_app_number] => 17/888641
[patent_app_country] => US
[patent_app_date] => 2022-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8446
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888641
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/888641 | Optimized storage charge loss management | Aug 15, 2022 | Issued |
Array
(
[id] => 20080574
[patent_doc_number] => 12354649
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-08
[patent_title] => Signal routing between memory die and logic die for performing operations
[patent_app_type] => utility
[patent_app_number] => 17/885325
[patent_app_country] => US
[patent_app_date] => 2022-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6235
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885325
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/885325 | Signal routing between memory die and logic die for performing operations | Aug 9, 2022 | Issued |
Array
(
[id] => 20080577
[patent_doc_number] => 12354652
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-08
[patent_title] => Memory device applying plural different read voltages to a word line in a read operation
[patent_app_type] => utility
[patent_app_number] => 17/885382
[patent_app_country] => US
[patent_app_date] => 2022-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 106
[patent_figures_cnt] => 119
[patent_no_of_words] => 50051
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 335
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885382
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/885382 | Memory device applying plural different read voltages to a word line in a read operation | Aug 9, 2022 | Issued |
Array
(
[id] => 18039730
[patent_doc_number] => 20220383947
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 17/818386
[patent_app_country] => US
[patent_app_date] => 2022-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9448
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818386
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/818386 | Static random access memory with write assist circuit | Aug 8, 2022 | Issued |
Array
(
[id] => 19552742
[patent_doc_number] => 12136453
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-05
[patent_title] => Systems, methods and media of optimization of temporary read errors in 3D NAND memory devices
[patent_app_type] => utility
[patent_app_number] => 17/879593
[patent_app_country] => US
[patent_app_date] => 2022-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 9742
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879593
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/879593 | Systems, methods and media of optimization of temporary read errors in 3D NAND memory devices | Aug 1, 2022 | Issued |
Array
(
[id] => 18958671
[patent_doc_number] => 20240046998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-08
[patent_title] => 3D NAND MEMORY WITH BUILT-IN CAPACITOR
[patent_app_type] => utility
[patent_app_number] => 17/879356
[patent_app_country] => US
[patent_app_date] => 2022-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12043
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879356
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/879356 | 3D NAND memory with built-in capacitor | Aug 1, 2022 | Issued |
Array
(
[id] => 18008201
[patent_doc_number] => 20220366968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-17
[patent_title] => SRAM-BASED IN-MEMORY COMPUTING MACRO USING ANALOG COMPUTATION SCHEME
[patent_app_type] => utility
[patent_app_number] => 17/816442
[patent_app_country] => US
[patent_app_date] => 2022-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13229
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17816442
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/816442 | SRAM-based in-memory computing macro using analog computation scheme | Jul 31, 2022 | Issued |
Array
(
[id] => 18514371
[patent_doc_number] => 20230230626
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-20
[patent_title] => PAGE BUFFER, MEMORY DEVICE HAVING PAGE BUFFER, AND METHOD OF OPERATING MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/876396
[patent_app_country] => US
[patent_app_date] => 2022-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9533
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876396
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/876396 | Page buffer, memory device having page buffer, and method of operating memory device | Jul 27, 2022 | Issued |
Array
(
[id] => 19000948
[patent_doc_number] => 11917826
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-27
[patent_title] => Semiconductor memory device with three-dimensional memory cells
[patent_app_type] => utility
[patent_app_number] => 17/868315
[patent_app_country] => US
[patent_app_date] => 2022-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 4691
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 559
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868315
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/868315 | Semiconductor memory device with three-dimensional memory cells | Jul 18, 2022 | Issued |
Array
(
[id] => 17985744
[patent_doc_number] => 20220351781
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => METHOD AND APPARATUS FOR DATA ERASE IN MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/866999
[patent_app_country] => US
[patent_app_date] => 2022-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9493
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866999
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/866999 | Method and apparatus for data erase in memory devices | Jul 17, 2022 | Issued |
Array
(
[id] => 18998897
[patent_doc_number] => 11915750
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-27
[patent_title] => Memory device and method for operating the same
[patent_app_type] => utility
[patent_app_number] => 17/862391
[patent_app_country] => US
[patent_app_date] => 2022-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 10362
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17862391
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/862391 | Memory device and method for operating the same | Jul 10, 2022 | Issued |
Array
(
[id] => 18898356
[patent_doc_number] => 20240013841
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-11
[patent_title] => CLOCK-GENERATING CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 17/861992
[patent_app_country] => US
[patent_app_date] => 2022-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3903
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861992
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/861992 | Clock-generating circuit | Jul 10, 2022 | Issued |
Array
(
[id] => 19796085
[patent_doc_number] => 12237050
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-25
[patent_title] => Three-dimensional (3-D) write assist scheme for memory cells
[patent_app_type] => utility
[patent_app_number] => 17/859545
[patent_app_country] => US
[patent_app_date] => 2022-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 13733
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17859545
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/859545 | Three-dimensional (3-D) write assist scheme for memory cells | Jul 6, 2022 | Issued |