Search

Mandish K. Randhawa

Examiner (ID: 12075, Phone: (571)270-5650 , Office: P/2475 )

Most Active Art Unit
2477
Art Unit(s)
2419, 2415, 2475, 2477
Total Applications
630
Issued Applications
361
Pending Applications
97
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18047706 [patent_doc_number] => 11521664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Memory device with tunable probabilistic state [patent_app_type] => utility [patent_app_number] => 16/933132 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6499 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16933132 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/933132
Memory device with tunable probabilistic state Jul 19, 2020 Issued
Array ( [id] => 16715811 [patent_doc_number] => 20210082958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => MEMORY CELL ARRANGEMENT AND METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 16/929660 [patent_app_country] => US [patent_app_date] => 2020-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16929660 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/929660
Memory cell arrangement and methods thereof Jul 14, 2020 Issued
Array ( [id] => 16759574 [patent_doc_number] => 10978129 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-13 [patent_title] => Memory cell, memory cell arrangement and methods thereof [patent_app_type] => utility [patent_app_number] => 16/930126 [patent_app_country] => US [patent_app_date] => 2020-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 12052 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16930126 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/930126
Memory cell, memory cell arrangement and methods thereof Jul 14, 2020 Issued
Array ( [id] => 17018190 [patent_doc_number] => 11087835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Memory device latch circuitry [patent_app_type] => utility [patent_app_number] => 16/927682 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5203 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927682 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927682
Memory device latch circuitry Jul 12, 2020 Issued
Array ( [id] => 17018507 [patent_doc_number] => 11088153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Integrated arrangements of pull-up transistors and pull-down transistors, and integrated static memory [patent_app_type] => utility [patent_app_number] => 16/927717 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4991 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927717 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927717
Integrated arrangements of pull-up transistors and pull-down transistors, and integrated static memory Jul 12, 2020 Issued
Array ( [id] => 16402075 [patent_doc_number] => 20200342933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => MEMORY DEVICES WITH SELECTIVE PAGE-BASED REFRESH [patent_app_type] => utility [patent_app_number] => 16/926582 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16926582 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/926582
Memory devices with selective page-based refresh Jul 9, 2020 Issued
Array ( [id] => 17210469 [patent_doc_number] => 11170844 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-09 [patent_title] => Ultra-low supply-voltage static random-access memory (SRAM) with 8-transistor cell with P and N pass gates to same bit lines [patent_app_type] => utility [patent_app_number] => 16/922087 [patent_app_country] => US [patent_app_date] => 2020-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4953 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922087 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/922087
Ultra-low supply-voltage static random-access memory (SRAM) with 8-transistor cell with P and N pass gates to same bit lines Jul 6, 2020 Issued
Array ( [id] => 17653167 [patent_doc_number] => 11355910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Systems and methods for detecting and identifying arcing based on numerical analysis [patent_app_type] => utility [patent_app_number] => 16/921594 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5751 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921594 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/921594
Systems and methods for detecting and identifying arcing based on numerical analysis Jul 5, 2020 Issued
Array ( [id] => 17062927 [patent_doc_number] => 11107536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Apparatus for determining data states of memory cells [patent_app_type] => utility [patent_app_number] => 16/916216 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 9537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916216 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/916216
Apparatus for determining data states of memory cells Jun 29, 2020 Issued
Array ( [id] => 16715337 [patent_doc_number] => 20210082484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => MAGNETIC MEMORY [patent_app_type] => utility [patent_app_number] => 16/914511 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914511 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/914511
Magnetic memory Jun 28, 2020 Issued
Array ( [id] => 16515802 [patent_doc_number] => 20200395060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => HOST APPARATUS AND EXTENSION DEVICE [patent_app_type] => utility [patent_app_number] => 16/913027 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913027 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/913027
Host apparatus and extension device Jun 25, 2020 Issued
Array ( [id] => 16880932 [patent_doc_number] => 11031088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Hot-cold VTH mismatch using VREAD modulation [patent_app_type] => utility [patent_app_number] => 16/909830 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 12794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909830 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/909830
Hot-cold VTH mismatch using VREAD modulation Jun 22, 2020 Issued
Array ( [id] => 16865995 [patent_doc_number] => 11024749 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-01 [patent_title] => Dual channel transistor device and methods of forming the same [patent_app_type] => utility [patent_app_number] => 16/901057 [patent_app_country] => US [patent_app_date] => 2020-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 8592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901057 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/901057
Dual channel transistor device and methods of forming the same Jun 14, 2020 Issued
Array ( [id] => 17093111 [patent_doc_number] => 11121309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Magnetic memory devices including magnetic tunnel junctions [patent_app_type] => utility [patent_app_number] => 16/901866 [patent_app_country] => US [patent_app_date] => 2020-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901866 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/901866
Magnetic memory devices including magnetic tunnel junctions Jun 14, 2020 Issued
Array ( [id] => 18052475 [patent_doc_number] => 11525851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Capacitive structure [patent_app_type] => utility [patent_app_number] => 16/897777 [patent_app_country] => US [patent_app_date] => 2020-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3559 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16897777 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/897777
Capacitive structure Jun 9, 2020 Issued
Array ( [id] => 19198885 [patent_doc_number] => 11996133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Memory circuit using oxide semiconductor [patent_app_type] => utility [patent_app_number] => 17/618993 [patent_app_country] => US [patent_app_date] => 2020-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 28 [patent_no_of_words] => 20034 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17618993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/618993
Memory circuit using oxide semiconductor Jun 8, 2020 Issued
Array ( [id] => 16973422 [patent_doc_number] => 11069401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Memory with symmetric read current profile and read method thereof [patent_app_type] => utility [patent_app_number] => 16/895069 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7266 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16895069 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/895069
Memory with symmetric read current profile and read method thereof Jun 7, 2020 Issued
Array ( [id] => 16936439 [patent_doc_number] => 20210202328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => METHODS AND APPARATUSES TO WAFER-LEVEL TEST ADJACENT SEMICONDUCTOR DIE [patent_app_type] => utility [patent_app_number] => 16/896120 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16896120 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/896120
Methods and apparatuses to wafer-level test adjacent semiconductor die Jun 7, 2020 Issued
Array ( [id] => 17040909 [patent_doc_number] => 20210257545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => MAGNETIC MEMORY STRUCTURE AND DEVICE [patent_app_type] => utility [patent_app_number] => 16/893877 [patent_app_country] => US [patent_app_date] => 2020-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16893877 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/893877
Magnetic memory structure and device Jun 4, 2020 Issued
Array ( [id] => 17107669 [patent_doc_number] => 11127897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Nonvolatile memory cells having an embedded selection element and nonvolatile memory cell arrays including the nonvolatile memory cells [patent_app_type] => utility [patent_app_number] => 16/891291 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 19378 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891291 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/891291
Nonvolatile memory cells having an embedded selection element and nonvolatile memory cell arrays including the nonvolatile memory cells Jun 2, 2020 Issued
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