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Mandish K. Randhawa

Examiner (ID: 12075, Phone: (571)270-5650 , Office: P/2475 )

Most Active Art Unit
2477
Art Unit(s)
2419, 2415, 2475, 2477
Total Applications
630
Issued Applications
361
Pending Applications
97
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14827367 [patent_doc_number] => 10410694 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-10 [patent_title] => High bandwidth chip-to-chip interface using HBM physical interface [patent_app_type] => utility [patent_app_number] => 16/048084 [patent_app_country] => US [patent_app_date] => 2018-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 32 [patent_no_of_words] => 7114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16048084 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/048084
High bandwidth chip-to-chip interface using HBM physical interface Jul 26, 2018 Issued
Array ( [id] => 14737951 [patent_doc_number] => 10388384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Determining data states of memory cells [patent_app_type] => utility [patent_app_number] => 16/043259 [patent_app_country] => US [patent_app_date] => 2018-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 9470 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16043259 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/043259
Determining data states of memory cells Jul 23, 2018 Issued
Array ( [id] => 14063505 [patent_doc_number] => 10236053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-19 [patent_title] => Method and circuit device incorporating time-to-transition signal node sensing [patent_app_type] => utility [patent_app_number] => 16/040442 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 27416 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16040442 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/040442
Method and circuit device incorporating time-to-transition signal node sensing Jul 18, 2018 Issued
Array ( [id] => 13613051 [patent_doc_number] => 20180358075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => TIME-BASED ACCESS OF A MEMORY CELL [patent_app_type] => utility [patent_app_number] => 16/032398 [patent_app_country] => US [patent_app_date] => 2018-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16032398 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/032398
Time-based access of a memory cell Jul 10, 2018 Issued
Array ( [id] => 16773743 [patent_doc_number] => 10984861 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-20 [patent_title] => Reference circuits and methods for resistive memories [patent_app_type] => utility [patent_app_number] => 16/032012 [patent_app_country] => US [patent_app_date] => 2018-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 6672 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16032012 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/032012
Reference circuits and methods for resistive memories Jul 9, 2018 Issued
Array ( [id] => 13878201 [patent_doc_number] => 20190035441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => VARIABLE FILTER CAPACITANCE [patent_app_type] => utility [patent_app_number] => 16/020834 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15992 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16020834 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/020834
Variable filter capacitance Jun 26, 2018 Issued
Array ( [id] => 13878225 [patent_doc_number] => 20190035453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => MEMORY DEVICES WITH SELECTIVE PAGE-BASED REFRESH [patent_app_type] => utility [patent_app_number] => 16/019483 [patent_app_country] => US [patent_app_date] => 2018-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16019483 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/019483
Memory devices with selective page-based refresh Jun 25, 2018 Issued
Array ( [id] => 13847493 [patent_doc_number] => 20190027231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/015941 [patent_app_country] => US [patent_app_date] => 2018-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16015941 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/015941
Controller to detect malfunctioning address of memory device Jun 21, 2018 Issued
Array ( [id] => 13484981 [patent_doc_number] => 20180294033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/009535 [patent_app_country] => US [patent_app_date] => 2018-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16009535 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/009535
Semiconductor device Jun 14, 2018 Issued
Array ( [id] => 14645479 [patent_doc_number] => 10367493 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-30 [patent_title] => Duty cycle and skew correction for output signals generated in source synchronous systems [patent_app_type] => utility [patent_app_number] => 16/008640 [patent_app_country] => US [patent_app_date] => 2018-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 37582 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16008640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/008640
Duty cycle and skew correction for output signals generated in source synchronous systems Jun 13, 2018 Issued
Array ( [id] => 14828013 [patent_doc_number] => 10411022 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-10 [patent_title] => SRAM structure [patent_app_type] => utility [patent_app_number] => 16/008302 [patent_app_country] => US [patent_app_date] => 2018-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16008302 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/008302
SRAM structure Jun 13, 2018 Issued
Array ( [id] => 14617955 [patent_doc_number] => 10361690 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-23 [patent_title] => Duty cycle and skew correction for output signals generated in source synchronous systems [patent_app_type] => utility [patent_app_number] => 16/008678 [patent_app_country] => US [patent_app_date] => 2018-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 37585 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16008678 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/008678
Duty cycle and skew correction for output signals generated in source synchronous systems Jun 13, 2018 Issued
Array ( [id] => 14768637 [patent_doc_number] => 10395719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Memory device driving matching lines according to priority [patent_app_type] => utility [patent_app_number] => 16/005880 [patent_app_country] => US [patent_app_date] => 2018-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16005880 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/005880
Memory device driving matching lines according to priority Jun 11, 2018 Issued
Array ( [id] => 14491549 [patent_doc_number] => 10332572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Memory device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/005698 [patent_app_country] => US [patent_app_date] => 2018-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 91 [patent_no_of_words] => 5090 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16005698 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/005698
Memory device and manufacturing method thereof Jun 11, 2018 Issued
Array ( [id] => 13629865 [patent_doc_number] => 20180366485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => 3-Dimensional NOR Strings with Segmented Shared Source Regions [patent_app_type] => utility [patent_app_number] => 16/006612 [patent_app_country] => US [patent_app_date] => 2018-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16006612 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/006612
3-dimensional nor strings with segmented shared source regions Jun 11, 2018 Issued
Array ( [id] => 14919873 [patent_doc_number] => 10431263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Simulating access lines [patent_app_type] => utility [patent_app_number] => 15/997389 [patent_app_country] => US [patent_app_date] => 2018-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 30460 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15997389 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/997389
Simulating access lines Jun 3, 2018 Issued
Array ( [id] => 13451315 [patent_doc_number] => 20180277200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => METHODS OF OPERATING A MEMORY WITH REDISTRIBUTION OF RECEIVED DATA [patent_app_type] => utility [patent_app_number] => 15/993968 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993968 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/993968
Methods of operating a memory with redistribution of received data May 30, 2018 Issued
Array ( [id] => 13784967 [patent_doc_number] => 20190006022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => APPARATUS FOR MEMORY DEVICE TESTING AND FIELD APPLICATIONS [patent_app_type] => utility [patent_app_number] => 15/993709 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993709 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/993709
Apparatus for memory device testing and field applications May 30, 2018 Issued
Array ( [id] => 14603059 [patent_doc_number] => 10354723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Memory device and method for programming the same [patent_app_type] => utility [patent_app_number] => 15/992940 [patent_app_country] => US [patent_app_date] => 2018-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 11858 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15992940 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/992940
Memory device and method for programming the same May 29, 2018 Issued
Array ( [id] => 14491621 [patent_doc_number] => 10332608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Memory block usage based on block location relative to array edge [patent_app_type] => utility [patent_app_number] => 15/992229 [patent_app_country] => US [patent_app_date] => 2018-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15992229 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/992229
Memory block usage based on block location relative to array edge May 29, 2018 Issued
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