
Mandish K. Randhawa
Examiner (ID: 12075, Phone: (571)270-5650 , Office: P/2475 )
| Most Active Art Unit | 2477 |
| Art Unit(s) | 2419, 2415, 2475, 2477 |
| Total Applications | 630 |
| Issued Applications | 361 |
| Pending Applications | 97 |
| Abandoned Applications | 193 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12206979
[patent_doc_number] => 20180052205
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-22
[patent_title] => 'METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING THRESHOLD VOLTAGE MEASUREMENT CIRCUITRY'
[patent_app_type] => utility
[patent_app_number] => 15/678658
[patent_app_country] => US
[patent_app_date] => 2017-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 6267
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678658
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/678658 | Method for making a semiconductor device including threshold voltage measurement circuitry | Aug 15, 2017 | Issued |
Array
(
[id] => 13282855
[patent_doc_number] => 10153018
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-11
[patent_title] => Ferroelectric memory cells
[patent_app_type] => utility
[patent_app_number] => 15/678978
[patent_app_country] => US
[patent_app_date] => 2017-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 27
[patent_no_of_words] => 21651
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678978
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/678978 | Ferroelectric memory cells | Aug 15, 2017 | Issued |
Array
(
[id] => 13111513
[patent_doc_number] => 10074414
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-11
[patent_title] => Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory
[patent_app_type] => utility
[patent_app_number] => 15/679016
[patent_app_country] => US
[patent_app_date] => 2017-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 10670
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679016
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/679016 | Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory | Aug 15, 2017 | Issued |
Array
(
[id] => 14095279
[patent_doc_number] => 10243560
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-26
[patent_title] => Maintaining slew rate while loading flash memory dies
[patent_app_type] => utility
[patent_app_number] => 15/675010
[patent_app_country] => US
[patent_app_date] => 2017-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8292
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15675010
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/675010 | Maintaining slew rate while loading flash memory dies | Aug 10, 2017 | Issued |
Array
(
[id] => 12188495
[patent_doc_number] => 20180047431
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-15
[patent_title] => 'CONTROL DEVICE FOR CONTROLLING SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/674248
[patent_app_country] => US
[patent_app_date] => 2017-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6418
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15674248
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/674248 | Control device for controlling semiconductor memory device | Aug 9, 2017 | Issued |
Array
(
[id] => 13452019
[patent_doc_number] => 20180277552
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-27
[patent_title] => Floating memristor
[patent_app_type] => utility
[patent_app_number] => 15/674206
[patent_app_country] => US
[patent_app_date] => 2017-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3871
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15674206
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/674206 | Floating memristor | Aug 9, 2017 | Issued |
Array
(
[id] => 13111501
[patent_doc_number] => 10074408
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-11
[patent_title] => Bit line sense amplifier
[patent_app_type] => utility
[patent_app_number] => 15/674022
[patent_app_country] => US
[patent_app_date] => 2017-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8445
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15674022
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/674022 | Bit line sense amplifier | Aug 9, 2017 | Issued |
Array
(
[id] => 13070691
[patent_doc_number] => 10056129
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-08-21
[patent_title] => Cell bottom node reset in a memory array
[patent_app_type] => utility
[patent_app_number] => 15/674382
[patent_app_country] => US
[patent_app_date] => 2017-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 13492
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15674382
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/674382 | Cell bottom node reset in a memory array | Aug 9, 2017 | Issued |
Array
(
[id] => 13694819
[patent_doc_number] => 20170358364
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-14
[patent_title] => METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY
[patent_app_type] => utility
[patent_app_number] => 15/672318
[patent_app_country] => US
[patent_app_date] => 2017-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19090
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15672318
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/672318 | Method and apparatus for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory | Aug 8, 2017 | Issued |
Array
(
[id] => 12435771
[patent_doc_number] => 09978439
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-05-22
[patent_title] => Line defect detection circuit and semiconductor memory device including the same
[patent_app_type] => utility
[patent_app_number] => 15/662517
[patent_app_country] => US
[patent_app_date] => 2017-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6537
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15662517
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/662517 | Line defect detection circuit and semiconductor memory device including the same | Jul 27, 2017 | Issued |
Array
(
[id] => 12181425
[patent_doc_number] => 20180040361
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-08
[patent_title] => 'SEMICONDUCTOR DEVICES AND INTEGRATED CIRCUITS INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/662525
[patent_app_country] => US
[patent_app_date] => 2017-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 9828
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15662525
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/662525 | Semiconductor devices and integrated circuits including the same | Jul 27, 2017 | Issued |
Array
(
[id] => 13187627
[patent_doc_number] => 10109339
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-10-23
[patent_title] => Memory devices with selective page-based refresh
[patent_app_type] => utility
[patent_app_number] => 15/663641
[patent_app_country] => US
[patent_app_date] => 2017-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 6085
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15663641
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/663641 | Memory devices with selective page-based refresh | Jul 27, 2017 | Issued |
Array
(
[id] => 12188508
[patent_doc_number] => 20180047444
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-15
[patent_title] => 'MEMORY SYSTEM WITH READ THRESHOLD ESTIMATION AND OPERATING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/663527
[patent_app_country] => US
[patent_app_date] => 2017-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7374
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15663527
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/663527 | Memory system with read threshold estimation and operating method thereof | Jul 27, 2017 | Issued |
Array
(
[id] => 13042865
[patent_doc_number] => 10043572
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-08-07
[patent_title] => VSS bitcell sleep scheme involving modified bitcell for terminating sleep regions
[patent_app_type] => utility
[patent_app_number] => 15/663096
[patent_app_country] => US
[patent_app_date] => 2017-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8108
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15663096
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/663096 | VSS bitcell sleep scheme involving modified bitcell for terminating sleep regions | Jul 27, 2017 | Issued |
Array
(
[id] => 13018763
[patent_doc_number] => 10032496
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-07-24
[patent_title] => Variable filter capacitance
[patent_app_type] => utility
[patent_app_number] => 15/662218
[patent_app_country] => US
[patent_app_date] => 2017-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 15947
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15662218
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/662218 | Variable filter capacitance | Jul 26, 2017 | Issued |
Array
(
[id] => 12033796
[patent_doc_number] => 20170323895
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-09
[patent_title] => 'ONE-TIME PROGRAMMING CELL'
[patent_app_type] => utility
[patent_app_number] => 15/659355
[patent_app_country] => US
[patent_app_date] => 2017-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 5575
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15659355
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/659355 | One-time programming cell | Jul 24, 2017 | Issued |
Array
(
[id] => 14332583
[patent_doc_number] => 10297315
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-21
[patent_title] => Resistive memory accelerator
[patent_app_type] => utility
[patent_app_number] => 15/657288
[patent_app_country] => US
[patent_app_date] => 2017-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 8251
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15657288
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/657288 | Resistive memory accelerator | Jul 23, 2017 | Issued |
Array
(
[id] => 14252575
[patent_doc_number] => 10276494
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-30
[patent_title] => One time programmable memory cell and memory array
[patent_app_type] => utility
[patent_app_number] => 15/654526
[patent_app_country] => US
[patent_app_date] => 2017-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4237
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15654526
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/654526 | One time programmable memory cell and memory array | Jul 18, 2017 | Issued |
Array
(
[id] => 12005161
[patent_doc_number] => 20170309315
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-26
[patent_title] => 'SIMULATING ACCESS LINES'
[patent_app_type] => utility
[patent_app_number] => 15/645238
[patent_app_country] => US
[patent_app_date] => 2017-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 33050
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15645238
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/645238 | Simulating access lines | Jul 9, 2017 | Issued |
Array
(
[id] => 12778165
[patent_doc_number] => 20180151223
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-31
[patent_title] => PHASE-CHANGE MEMORY DEVICE WITH DRIVE CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 15/639540
[patent_app_country] => US
[patent_app_date] => 2017-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6875
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15639540
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/639540 | Phase-change memory device with drive circuit | Jun 29, 2017 | Issued |