Mandish K. Randhawa

Array ( [id] => 12848368 [patent_doc_number] => 20180174629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/638516 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15638516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13782741 [patent_doc_number] => 20190004909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => STACKED MEMORY CHIP DEVICE WITH ENHANCED DATA PROTECTION CAPABILITY [patent_app_type] => utility [patent_app_number] => 15/640182 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13769035 [patent_doc_number] => 10176864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Static random access memory circuits [patent_app_type] => utility [patent_app_number] => 15/633167 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15633167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12129048 [patent_doc_number] => 20180012635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'CIRCUIT FOR SELECTING A POWER SUPPLY VOLTAGE HAVING A CONTROLLED TRANSITION' [patent_app_type] => utility [patent_app_number] => 15/628074 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9371 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13629237 [patent_doc_number] => 20180366171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => VERTICAL SELECTOR FOR THREE-DIMENSIONAL MEMORY WITH PLANAR MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 15/627175 [patent_app_country] => US [patent_app_date] => 2017-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12799969 [patent_doc_number] => 20180158492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => STORAGE DEVICE OPERATING DIFFERENTLY ACCORDING TO TEMPERATURE OF MEMORY [patent_app_type] => utility [patent_app_number] => 15/626574 [patent_app_country] => US [patent_app_date] => 2017-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13607 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15626574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12229642 [patent_doc_number] => 09916888 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-13 [patent_title] => 'System for measuring access time of memory' [patent_app_type] => utility [patent_app_number] => 15/622566 [patent_app_country] => US [patent_app_date] => 2017-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 11309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15622566 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13631193 [patent_doc_number] => 20180367149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => PURE MEMRISTIVE LOGIC GATE [patent_app_type] => utility [patent_app_number] => 15/622090 [patent_app_country] => US [patent_app_date] => 2017-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15622090 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12534264 [patent_doc_number] => 10008278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-26 [patent_title] => Memory block usage based on block location relative to array edge [patent_app_type] => utility [patent_app_number] => 15/619494 [patent_app_country] => US [patent_app_date] => 2017-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7040 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15619494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14204603 [patent_doc_number] => 10269420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Memory with symmetric read current profile and read method thereof [patent_app_type] => utility [patent_app_number] => 15/619084 [patent_app_country] => US [patent_app_date] => 2017-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15619084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13613047 [patent_doc_number] => 20180358073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => TIME-BASED ACCESS OF A MEMORY CELL [patent_app_type] => utility [patent_app_number] => 15/619158 [patent_app_country] => US [patent_app_date] => 2017-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -44 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15619158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13070735 [patent_doc_number] => 10056151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-21 [patent_title] => Multi-read only memory finite state machine [patent_app_type] => utility [patent_app_number] => 15/612934 [patent_app_country] => US [patent_app_date] => 2017-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15612934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12416349 [patent_doc_number] => 09972396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-15 [patent_title] => System and method for programming a memory device with multiple writes without an intervening erase [patent_app_type] => utility [patent_app_number] => 15/610870 [patent_app_country] => US [patent_app_date] => 2017-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9230 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15610870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13029557 [patent_doc_number] => 10037400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Integrated circuit manufacturing process for aligning threshold voltages of transistors [patent_app_type] => utility [patent_app_number] => 15/611628 [patent_app_country] => US [patent_app_date] => 2017-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4594 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15611628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12054283 [patent_doc_number] => 20170330626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => '3D NAND MEMORY Z-DECODER' [patent_app_type] => utility [patent_app_number] => 15/606493 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15606493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12314739 [patent_doc_number] => 09941299 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-10 [patent_title] => Three-dimensional ferroelectric memory device and method of making thereof [patent_app_type] => utility [patent_app_number] => 15/604092 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11345 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15604092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13145379 [patent_doc_number] => 10090027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Memory system with low read power [patent_app_type] => utility [patent_app_number] => 15/603478 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3839 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12033591 [patent_doc_number] => 20170323690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/599713 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9252 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599713 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12101874 [patent_doc_number] => 09858972 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-02 [patent_title] => 'Semiconductor devices' [patent_app_type] => utility [patent_app_number] => 15/597672 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12086 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15597672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13005621 [patent_doc_number] => 10026481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/597294 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 17967 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15597294 [rel_patent_id] =>[rel_patent_doc_number] =>)